Run design rule check
easyeda_drc_runRun the native design rule check for PCB design to identify rule violations; returns counts of errors, warnings, and info per severity.
Instructions
Run the native design rule check (DRC): same as clicking "Check DRC" in EasyEDA Pro, so the bottom DRC panel opens/refreshes in the user's window as a visible side effect. Returns coarse per-severity counts only — which specific wire/net/component is affected is shown only in EasyEDA Pro's own DRC panel.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| rules | No | ||
| projectId | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| passed | Yes | ||
| project_id | Yes | ||
| violations | Yes | ||
| error_count | Yes | ||
| not_available | No | ||
| warning_count | Yes | ||
| total_violations | Yes |