Get active PCB design rules
easyeda_board_design_rulesRead the active EasyEDA DRC profile and global safe-spacing matrix so you can verify board clearances; net-class membership and per-net overrides are reported separately.
Instructions
Read the active EasyEDA DRC profile and its global safe-spacing matrix. Net-class membership and per-net overrides are reported separately and are not inferred.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"projectId": "<projectId>"
},
"name": "easyeda_board_design_rules"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| projectId | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| error | No | ||
| project_id | Yes | ||
| data_source | Yes | ||
| not_available | No | ||
| has_clearance_rules | No | ||
| clearance_rule_count | No | ||
| minimum_clearance_mm | No | ||
| active_spacing_matrices | Yes | ||
| active_rule_configuration_name | No |