vcc_force
Force a signal to a specific value, with optional timing, to override or set initial conditions in HDL simulation.
Instructions
Force signal to value (e.g. force sim.top.rst 1 0; force sim.top.clk 0 50ns).
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| signal | Yes | ||
| value | Yes | ||
| time | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||