vcc_examine
Examine a signal's value in a hardware simulation, at an optional time point, with selectable radix representation (decimal, binary, hexadecimal, unsigned, octal).
Instructions
Examine the value of a signal, optionally at a specific simulation time.
signal: dot-separated hierarchical path with "sim." prefix e.g. sim.testbench.u1.my_signal time: simulation time e.g. "400 ns" (omit for current time) radix: decimal (default), binary, hexadecimal, unsigned, octal
The returned value may include a size/radix annotation e.g. "4'd3" (4-bit vector, decimal value 3). If Visualizer is not configured to annotate, the plain value is returned e.g. "3". Signal must be last in the examine command; this tool enforces that.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| signal | Yes | ||
| time | No | ||
| radix | No | decimal |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||