list_design_rules
Retrieve .edru and .estackup files for common JLCPCB fab processes and copy them to a reachable folder to load in Fusion's DRC dialog or Layer Stack Manager.
Instructions
Design-rule (.edru) and stackup (.estackup) files shipped with this server for common fab processes (every JLCPCB 4- and 6-layer impedance stackup, and a 2-layer 1.6 mm board; built from JLC's published tables by tools/gen_jlc_stackups.py): copper layers, board thickness, dielectrics (thickness, Er) and the key clearances of each. Fusion cannot load rules from a script: load a .edru in the DRC dialog (Rules > Load; it carries its stackup too) or a .estackup in the Layer Stack Manager. copy_to copies the files into a folder you can reach from Fusion's file dialog (e.g. Downloads).
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| copy_to | No |