configure_bus_spi
Set a bus to SPI decoding and configure clock, data lines, polarity, bit order, frame sync, and display. Enables oscilloscope SPI bus analysis.
Instructions
Set Bus to SPI decoding and configure it (manual 3.4.13).
sclk: clock source CH1..CH4 or D0..D15 clk_slope: POSitive|NEGative clock edge sampled on miso / mosi: data line sources; each may be OFF but not both at once polarity: HIGH|LOW data polarity (high=1 / low=1) dbits: data width 4..32 bits (default 8) endian: MSB|LSB bit order (default MSB) mode: CS|TIMeout frame synchronization (default TIMeout) timeout_s: timeout frame gap in s, 8 ns..10 s (TIMeout mode only, must exceed the max clock pulse width) ss: chip-select line source CH1..CH4 or D0..D15 (CS mode only) ss_polarity: HIGH|LOW chip-select active level (CS mode only) display: enable the decoding bus
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| ss | No | ||
| bus | Yes | ||
| miso | No | ||
| mode | No | ||
| mosi | No | ||
| sclk | No | ||
| dbits | No | ||
| endian | No | ||
| display | No | ||
| polarity | No | ||
| clk_slope | No | ||
| timeout_s | No | ||
| ss_polarity | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |