verify_board
Grades a PCB with kicad-cli against routing and design-rule checks, returning PASS, FAIL, or INCOMPLETE with full unconnected-net and violation lists; only PASS confirms routed and done.
Instructions
The acceptance gate. Grades a board with real kicad-cli (three refilled runs, union of errors) and returns PASS, FAIL or INCOMPLETE plus the COMPLETE per-net unconnected list and the complete violation list. Only a PASS may be reported as routed or done.
parity: "required" (a missing or unannotated schematic, or one with stale instance paths, is INCOMPLETE) or "not_applicable" (give parity_reason, e.g. an imported board with no schematic). baseline: the dict from pin_rule_baseline. Without it the verdict is INCOMPLETE, because rule weakening (.kicad_dru severity ignore, rule_severities) would go unseen. FAIL takes precedence over INCOMPLETE. incomplete_reasons say why a verdict is INCOMPLETE. notes are informational hints (e.g. the units of one part disagree on DNP): they are never reasons and never change the verdict, so a note neither doubts a PASS nor excuses a FAIL or INCOMPLETE.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| parity | Yes | ||
| baseline | No | ||
| pcb_path | Yes | ||
| parity_reason | No |