List available KiCad tool groups (schematic, pcb, sourcing, ...) and whether each is currently loaded.

Load a tool group's tools into this session, e.g. 'sourcing', 'schematic', 'pcb', 'verification'.

Unload a tool group's tools to free up the session's tool-schema budget.

The acceptance gate. Grades a board with real kicad-cli (three refilled runs, union of errors) and returns PASS, FAIL or INCOMPLETE plus the COMPLETE per-net unconnected list and the complete violation list. Only a PASS may be reported as routed or done.

parity: "required" (a missing or unannotated schematic, or one with stale instance paths, is INCOMPLETE) or "not_applicable" (give parity_reason, e.g. an imported board with no schematic). baseline: the dict from pin_rule_baseline. Without it the verdict is INCOMPLETE, because rule weakening (.kicad_dru severity ignore, rule_severities) would go unseen. FAIL takes precedence over INCOMPLETE. incomplete_reasons say why a verdict is INCOMPLETE. notes are informational hints (e.g. the units of one part disagree on DNP): they are never reasons and never change the verdict, so a note neither doubts a PASS nor excuses a FAIL or INCOMPLETE.

Snapshot the rule settings verify_board grades against (rule severities, netclass limits, .kicad_dru severity clauses, ignored checks). Read-only: the caller stores the result and passes it as baseline. Pin before the work, not after it.

Dry run of input preparation: lists every copper-layer text (F.Cu/B.Cu gr_text) that would move to silkscreen, and returns a revision_token. Writes nothing.

Run this step once per board, BEFORE pin_rule_baseline and before any routing; never inside a routing attempt. Copper text it cannot handle (inner-layer text, text boxes) is listed under unhandled, and the input floor is then NOT a clean baseline. With nothing to move there is no token (status nothing_to_do). This tool gives no verdict: only verify_board does.

output_dir: new directory for the prepared project copy (default: sibling <project>_prepared); it must not be inside the source project or non-empty.

Apply a proposal from propose_input_preparation: writes a NEW prepared board revision (the source is untouched), re-pins the rule baseline on it and reports the input_floor (errors present before any routing; never waive them).

Runs once per board, BEFORE the pin_rule_baseline you use for routing, never inside an attempt: use the returned output_pcb and baseline from here on. Copper text it cannot handle is listed under unhandled; the floor is then NOT a clean baseline. The revision_token is single use. input_floor carries grading_status and certified: false, not a verdict (the prepared board's gate stays NOT_RUN/stale): only verify_board gives a verdict. pcb_path in the result is the prepared board (same as output_pcb); the board you passed in is source_pcb.

parity: "required" or "not_applicable" (give parity_reason), passed to the gate unchanged.

Dry run of the pour step: validates the requested power planes and returns a revision_token. Writes nothing and runs no router.

pours: {net name: copper layer}, one net per layer, e.g. {"GND": "B.Cu"}. A net that already has a pour on that layer is skipped. Run propose_input_preparation / confirm_input_preparation first (copper-layer text is refused by confirm), then pin_rule_baseline, then this step once, before routing signals. output_dir: a new directory (default sibling <project>_poured); not inside the source project. This tool gives no verdict: only verify_board does.

Run the plane router on a scratch copy of the board, grade its candidate, and only if accepted write a NEW board revision with the zone (plus any vias/tracks the plane script added); the source is untouched. The revision_token is single use.

baseline: the dict from pin_rule_baseline, REQUIRED (this step never pins silently; an empty baseline is refused as incomplete). Input preparation (propose_input_preparation) must have run first: a board with copper-layer text is refused.

What status poured proves: the candidate was graded by verify_board's gate, the zone is filled (measured in a kicad-cli refilled copy; the file on disk holds the outline only) and no pad was found isolated by the checks listed in the result. It does NOT prove the board is connected or complete: each pad in pads carries connectivity: proven|unproven (unproven pads, e.g. waiting for a via, and every open signal remain). Only verify_board certifies a board.

Cost per confirm: about 12 gate runs (kicad-cli DRC) plus connectivity runs, capped at 40 in total; expect minutes, not seconds. Over the cap a pad is never accepted unproven.

In the result, pcb_path is the new revision (same as output_pcb) and source_pcb is the board you passed in; both gates are stale until verify_board runs on the revision.

Dry run of importing footprints and nets from the project's schematic into the board (Update PCB from Schematic): lists every footprint and net that would be added and where new footprints are staged; writes nothing and returns a revision_token. Any footprint that cannot be resolved through the project fp-lib-table / installed libraries blocks the proposal (status blocked, no token) and is named. Staged footprints are not placed: placement is a separate step. schematic_path defaults to the board's own .kicad_sch; staging_origin is [x, y] in page mm (default: right of the Edge.Cuts box). Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Apply a propose_schematic_import proposal: writes a NEW board revision with the schematic's footprints and every pad net, verified by a fresh reload against the kicad-cli netlist; an unresolved footprint fails the whole confirm and nothing is written. The revision_token is single use. Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Dry run of setting the board's design rules (minimum clearance, track width, via diameter, via annular width, through-hole diameter, and named net classes with their nets) in the project's .kicad_pro; lists every value that would change, every loosening and every incoherence; writes nothing and returns a revision_token. Lengths are mm. A key absent from the project counts as KiCad's built-in default, never as unset. netclasses: [{name, clearance?, track_width?, via_diameter?, via_drill?, priority?, nets?: [exact net names]}]. allow_loosen: lowering a rule is refused unless this is true; set only after a human has read the listed items; never set it to get past a refusal on your own. allow_incoherent: a class value below a board minimum is refused unless this is true; set only after a human has read the listed items; never set it to get past a refusal on your own. Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Apply a propose_board_rules proposal: writes a NEW project revision with the rules, verified by a fresh reload, then pins the rule baseline of that revision and grades it (the grading field is not a verdict). Any rule change makes every earlier baseline pin and verdict void: use the returned baseline and re-run verify_board on output_pcb. The revision_token is single use. parity: "required" or "not_applicable" (give parity_reason), passed to the gate unchanged. Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Dry run of replacing the board outline (one rectangle, optional rounded corners) and adding mounting holes with copper keepouts; lists what would be replaced, which footprints would fall outside the new outline (reported, never moved) and any hole that touches existing items; writes nothing and returns a revision_token. outline: {x, y, width, height, corner_radius?} in mm. mounting_holes: [{reference, x, y, keepout_radius_mm, footprint?}]. origin: "page" (file coordinates, default) or "aux_axis" (relative to the board's aux axis origin). allow_overlap: a hole whose keepout touches footprints, tracks, vias, zones or another hole is refused unless this is true; set only after a human has read the listed items; never set it to get past a refusal on your own. Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Apply a propose_board_outline proposal: writes a NEW board revision with the outline and mounting holes, verified by a fresh reload and a kicad-cli outline check; copper pours under a new keepout need refilling before any pour or DRC figure means anything. The revision_token is single use. Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Dry run of raising every silkscreen text below the fab minimums (height and stroke) on a NEW revision; lists each text with its before and after size, and any text it cannot handle under unhandled; writes nothing and returns a revision_token (none when there is nothing to raise). It never moves, hides or re-layers text: overlaps the larger text may create are for verify_board to report. min_height_mm default 1.0, min_thickness_mm default 0.15. Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Apply a propose_silkscreen_minimums proposal: writes a NEW board revision with the raised text, verified by a fresh reload against the plan. The revision_token is single use. Order for a project: import_from_schematic -> board_outline -> board_rules -> input_preparation -> silkscreen_minimums -> pin_rule_baseline -> pour step -> routing. Every confirm writes a NEW board revision beside the source (the source is untouched) and returns it as output_pcb (also pcb_path; the board you passed in is source_pcb): continue from that path. Both gates are stale until verify_board runs; only verify_board certifies.

Scaffold a new KiCad project: .kicad_pro, blank .kicad_sch, blank .kicad_pcb.

Open an existing KiCad project and summarize its schematic/PCB contents.