Trace XNET from a pin
query_xnet_by_pin_nameTrace full XNET connectivity from a component pin (REFDES.PIN) through series components to identify the whole electrical node, stopping at power/ground nets and optionally excluding passive types.
Instructions
Get full XNET connectivity starting from a component pin, named REFDES.PIN (e.g. U1.A5, R10.1). Traces through series components, so the result is the whole electrical node; circuit_hash identifies unique topologies. Traversal stops at power and ground nets, recognised by name (VCC*, VDD*, 3V3, GND*, VSS*, ...) or by carrying more than 40 pins; a rail named outside that is traversed like a signal, and visited_nets names every net the result crossed. skip_types leaves series passives out, for example skip_types=['C','L','R']. A pin on no net reads as the net NC and returns an empty result. component_notes names the parts with no MPN. Rejects pins connected to ground nets (GND, AGND, DGND, etc.) with an error.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| design | Yes | Path to design file | |
| pin_name | Yes | Pin spec: REFDES.PIN (e.g., U2.10, U1.A5) | |
| skip_types | No | Component prefixes to exclude | |
| include_dns | No | Include DNS components | |
| design_variant | No | Design variant name from list_designs' design_variants. Required when the design records named variants, which are its only builds. <Default> (alias: default) is the one build of a design that records none |