Trace XNET from a net
query_xnet_by_net_nameRetrieves full extended-net connectivity for a named net by tracing through series components to return the complete electrical node, with optional component-type exclusions.
Instructions
Get full XNET (Extended Net) connectivity for a net. Traces through series components, so the result is the whole electrical node rather than the one net; circuit_hash identifies unique topologies. Traversal stops at power and ground nets, recognised by name (VCC*, VDD*, 3V3, GND*, VSS*, ...) or by carrying more than 40 pins. A rail named outside that, such as VDIO_LMS, is traversed like a signal, so a query that pulls up to one returns its whole pull-up network; visited_nets names every net the result crossed. skip_types leaves series passives out; skip_types=['C','L','R'] removes all three from the result. Rejects ground nets (GND, AGND, DGND, etc.) with an error. A name that matches no net exactly is matched ignoring leading and trailing whitespace, then as the 31-character name a PSTWRITER 16.6 Allegro export gives a longer net; notes says when that happened, and a name that could mean several nets returns them. component_notes names the parts with no MPN. If the net is not found, search_nets finds the name.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| design | Yes | Path to design file | |
| net_name | Yes | Net name. An exact match wins; otherwise it is matched ignoring leading and trailing whitespace, and for Cadence as a 31-character PSTWRITER 16.6 name | |
| skip_types | No | Component prefixes to exclude (e.g., ['C', 'L']) | |
| include_dns | No | Include DNS components | |
| design_variant | No | Design variant name from list_designs' design_variants. Required when the design records named variants, which are its only builds. <Default> (alias: default) is the one build of a design that records none |