pcb_generate
Generate a fully-wired .kicad_pcb from a declarative spec: auto-fetches EasyEDA pin maps, places footprints in bands, wires every net pad-to-pad, and draws the board outline.
Instructions
Generate a fully-wired .kicad_pcb from a declarative spec using KiCad's pcbnew Python API. Each component in the spec needs an LCSC C-number — the plugin auto-fetches pin maps from EasyEDA so your nets can reference pin NAMES (like 'GPIO10' or 'VCC') instead of numbers. First run may pause ~12 seconds per unique IC for EasyEDA's rate limit; results are cached in SQLite so subsequent runs are instant. The tool then auto-places footprints in three bands (connectors on top, ICs in middle, passives below), wires every net pad-to-pad, and draws a board outline. Result: a .kicad_pcb ready to open in KiCad or EasyEDA for routing. REQUIRES KiCad 8+ installed (pcbnew is KiCad-side Python).
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| spec | Yes | PCB spec with board/components/nets. See plugin docs for the full schema. | |
| lib_dir | No | Directory holding KiCad's stock .pretty footprint libraries. Normally omit it — the plugin finds KiCad's libraries on Linux, macOS, Windows and Flatpak, and honours KJLC_FOOTPRINT_DIR / KICAD*_FOOTPRINT_DIR. | |
| output_path | No | Optional output .kicad_pcb path. Defaults to the active project's .kicad_pcb. | |
| force_refresh | No | Bypass cached pin maps and refetch from EasyEDA. Slow (rate-limited to one request per 12s); use only when a cached map is known to be wrong. | |
| auto_fetch_pinmaps | No | Fetch pin-name to pad-number maps from EasyEDA for components that have an 'lcsc' field and no explicit 'pinmap'. Set false to work offline — nets must then reference bare pad numbers. |