"Understanding Requirement Analysis" matching MCP servers:

Enables MCP-compatible AI clients to operate a RIGOL MHO98 oscilloscope over USB, including configuration, waveform and measurement acquisition, FFT analysis, and protocol decoding.

Enables Android Automotive developers to explore and implement Vehicle Hardware Abstraction Layer (vHAL) properties with intelligent tools for property analysis, source code lookup, implementation guidance, and automated code generation for automotive systems like climate control and seat management.

Enables AI assistants to operate a Fishball7020/PlutoSky software-defined radio, including tuning, spectrum analysis, band scanning, IQ capture, FPGA filtering, and optional transmission.

Enables LLMs to control RIGOL oscilloscopes over SCPI via LAN or USB, including configuring channels/timebase/trigger, taking measurements, capturing waveforms and screenshots, decoding serial protocols, running FFT analysis, and controlling the built-in AFG.

AI-powered FPGA power estimation assistant that wraps Xilinx PDM API as MCP services for natural language power modeling and analysis.

Enables AI tools to perform full-featured embedded microcontroller debugging via pyOCD and CMSIS-DAP probes, including probe management, flashing, breakpoints, register/memory access, fault analysis, and RTT communication.

A Model Context Protocol (MCP) server that exposes lnav log file analysis capabilities to AI assistants, specifically optimized for Kvaser Plain Text Log Frame CAN bus log processing.

Enables LLMs to control a Nordic Power Profiler Kit II over USB serial for current capture (500 nA–2000 mA at 100 kSa/s plus 8 logic channels) and DUT power sourcing (0.8–5 V), with samples written to npz files. Also supports offline analysis such as statistics, activity/duty-cycle segmentation, and battery-life estimation.

Enables analysis of KiCad electronic schematics through natural language queries to search components, trace signal paths, explore connections, and analyze multi-board systems.

Enables AI agents to deterministically inspect, author, convert, validate, and diagnose Classical CAN and CAN FD databases and trace logs, including bit-layout validation, template generation, trace aggregation, ISO-TP/UDS reassembly, bus-health analysis, and reverse engineering.

Enables local analysis of FPGA synthesis diagnostics and Synopsys Synplify Pro reports, including parsing diagnostic messages and comparing warnings, resources, and preliminary timing reports across builds. It currently provides a limited prototype with read-only server and tool status and does not run synthesis or simulation.

Serial communication and protocol analysis MCP server that gives AI coding assistants direct access to serial ports for reading, writing, decoding, and capturing embedded device output.

Provides AI assistants with tools for Arm architecture development, migration, and optimization, including knowledge base search, code migration analysis, container inspection, assembly performance analysis, and workload performance testing.

Enables debugging of PlayStation games through DuckStation by providing MCP tools for execution control, register access, memory inspection, breakpoints, process management, and log analysis.

Enables an MCP client to configure a Saleae Logic MSO mixed-signal oscilloscope, run timed or edge-triggered captures, and retrieve measurements, decimated waveforms, and digital transitions directly from chat, with captures saved to disk for later re-analysis.

Remote automation server for AMD Vivado builds and analysis over SSH, enabling MCP clients to run synthesis, implementation, and debug without local toolchain.

Reverse-engineer Atari 8-bit binaries and ATR disk images with 6502 disassembly, symbol management, cross-reference analysis, and pattern matching tools.

Wraps Vector DaVinci Configurator 6/5 and DaVinci Developer Classic command-line tools into MCP tools so AI agents can validate, update, generate, compare, and inspect AUTOSAR projects with structured operations, background jobs, Groovy automation, ECUC analysis, version detection, and generated-file reporting.

A dynamic-analysis MCP server for reverse-engineering the Broadcom BCM6726b0 WiFi driver, enabling live GDB debugging of the QEMU dhd harness with breakpoints, stepping, and memory inspection.

Enables Large Language Models to act as co-debuggers for Texas Instruments embedded systems by providing real-time variable monitoring, memory manipulation, and motor control analysis through OpenOCD proxy architecture. Supports debugging TI microcontrollers with XDS110 debug probes while working alongside Code Composer Studio.

Provides a dependency-free MCP interface to the complete Keil µVision 5 (MDK) surface, enabling project and dependency modeling, CMSIS-Pack inspection, UV4 CLI/UVSOCK control, toolchain/image/debugger analysis, and license-free compilation and flashing. It also supports byte-faithful project-file editing and plain-language build diagnostics through 93 tools.

Enables AI agents such as Claude Code, Cursor, and Codex to safely drive a locally installed Xilinx Vivado through 32 MCP tools covering sessions, synthesis, implementation, timing, CDC, XDC, IP, waveform queries, and device programming. Provides structured timing/baseline evidence, offline VCD and report analysis, environment self-checks, and Chinese diagnostics for CRITICAL WARNINGs and timing issues.

Enables AI agents like Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado through 32 curated tools covering GUI/Tcl/attach sessions, synthesis, implementation, timing and CDC analysis, XDC and IP inspection, offline VCD waveform queries, bitstream generation, and device programming. It delivers structured timing evidence with baseline comparison, asynchronous run progress polling, bitstream safety checks, and Chinese-language diagnostics for CRITICAL WARNINGs, while general flows are handled through arbitrary Tcl execution.

An MCP server for EMBA firmware analysis that exposes structured security findings and tools to LLMs. It enables users to programmatically query, reason over, and correlate firmware analysis results such as kernel details, SBOMs, and attack paths.

Enables AI coding agents such as Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado across the full FPGA flow, with tools for sessions, synthesis, implementation, timing, CDC, XDC, IP, waveform querying, and device programming. It also provides structured timing evidence with baseline comparison, offline VCD analysis, evidence-driven workflow prompts, and a read-only doctor for environment self-checks.

Enables AI agents to drive a locally installed Xilinx Vivado through 32 curated tools covering sessions, synthesis, implementation, timing and CDC analysis, XDC constraints, IP inspection, waveform queries, and device programming, with structured evidence, environment self-checks, and evidence-gated workflow prompts. Supports GUI, headless Tcl, and attach session modes.

Enables AI coding agents to safely drive a locally installed Xilinx Vivado through curated tools covering sessions, synthesis, implementation, timing and CDC analysis, XDC/IP checks, offline waveform queries, and device programming, returning structured JSON evidence plus Chinese-language diagnostics of critical warnings. It also ships evidence-driven workflow prompts and skills, an environment self-check command, and GUI, headless Tcl, and attach session modes.

Enables AI coding agents such as Claude Code, Cursor, and Codex to safely drive a locally installed Xilinx Vivado through 32 curated tools covering sessions, synthesis, implementation, timing and CDC analysis, XDC/IP debugging, offline VCD waveform queries, and device programming. It provides structured timing evidence with baseline comparison, evidence-driven workflow prompts, environment self-checks via doctor, and Chinese-language diagnostics for CRITICAL WARNINGs and timing issues.

Enables AI coding agents such as Claude Code, Cursor, and Codex to safely drive a locally installed Xilinx Vivado through MCP tools covering sessions, synthesis, implementation, timing and CDC analysis, XDC constraints, IP, waveform queries, and device programming. Includes evidence-driven workflow prompts, environment self-checks, and Chinese-language diagnostics for timing and CRITICAL WARNING issues.

Enables AI coding agents such as Claude Code, Cursor, and Codex to drive a locally installed Xilinx Vivado across the full FPGA flow, from GUI, headless Tcl, or attached sessions through synthesis, implementation, timing and CDC analysis, waveform queries, and device programming. It exposes 32 curated tools plus evidence-driven workflow prompts that return structured timing/IO reports, Chinese-language CRITICAL WARNING diagnostics, and guarded bitstream generation.