"Kotlin RAG (Retrieval-Augmented Generation) implementation resources" matching MCP servers:

Provides read-only retrieval of STM32 datasheet and reference manual content with exact citations, page numbers, register details, and source hashes so Claude can answer questions or generate code from verified evidence.

MCP server for deterministic Vivado FPGA automation including project scaffolding, simulation, synthesis, implementation, and gated bitstream generation.

An MCP server for source-grounded, page-cited evidence retrieval tailored for embedded and firmware development, returning verbatim snippets with exact citations or 'no match' to prevent fabrications.

An MCP server for Nordic nRF Connect SDK development that enables users to list, read, and search documentation and sample code from the nrfconnect/sdk-nrf repository. It provides Claude with specialized tools to navigate SDK resources, source files, and configuration examples directly through the GitHub API.

MCP server providing embedded engineering calculators and code generators as tools for AI agents, enabling precise, deterministic embedded math and C code generation.

A headless MCP server that enables AI tools (like Claude Code) to read and analyze serial logs from embedded boards (ESP32, STM32) for firmware debugging, with read-only tools for log retrieval and a built-in web viewer.

MCP server for structured GB Studio 4.x project editing, enabling read/patch scripts, scenes, actors, triggers, variables; build ROMs; and sprite generation.

Provides LLMs with direct access to official vendor PDF documentation for electronics components (TI, ST, ADI) via a local SQLite full-text index and PDF retrieval tools.

MCP server that serves Qualcomm Yocto board specs from a git repo, enabling retrieval and validation of board specifications.

Enables Android Automotive developers to explore and implement Vehicle Hardware Abstraction Layer (vHAL) properties with intelligent tools for property analysis, source code lookup, implementation guidance, and automated code generation for automotive systems like climate control and seat management.

Enables AI coding assistants to perform complete headless STM32 embedded firmware development, including project creation, pin configuration, code generation, building, and flashing, by driving the official STM32 command-line toolchain.

MCP server that lets AI assistants control Siglent SDG waveform generators over a local network using natural language, supporting signal generation, modulation, sweep, burst, and arbitrary waveforms.

An MCP server that exposes RS232 serial port connectivity, enabling listing, opening, reading, and writing to serial ports via tools and resources.

Enables AI agents to turn natural-language hardware prompts into deterministic schematics and netlists, query live LCSC parts data, validate designs, calculate trace impedance, and estimate PCBA BOM costs through stdio MCP tools and resources.

Enables AI-assisted Pre820 EVE development by indexing EveApps samples and APIs to provide sample discovery, API guidance, scaffold generation, code validation, and build command generation.

An MCP server that lets AI coding agents drive the full STM32 development loop—code generation, build, flash, debug, serial monitoring, and fault diagnosis—end to end via CubeIDE, CubeMX, CubeProgrammer, OpenOCD, and GDB.

Enables AI tools to manage Renesas e2studio projects, including building, flashing, and debugging embedded code through MCP tools and resources.

MCP server that provides tools, resources, and prompts to help LLMs build Svelte UI components for Q-SYS systems, including discovering components and controls from a Q-SYS Core.

Enables automated generation of FreeRTOS embedded projects for chips like BK7252, STM32F4, and ESP32. Provides intelligent project structure creation, peripheral driver code generation, and complete embedded development workflows through natural language interaction.

Enables AI coding assistants to drive Xilinx Vivado through natural language, letting users open .xpr projects, run synthesis, implementation, and bitstream generation, inspect timing, resource, and clock reports, and launch simulations to read signal values or set breakpoints. It also exposes design hierarchy queries and arbitrary TCL execution, so FPGA design flows can be operated conversationally on Windows.