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  • A
    license
    A
    quality
    C
    maintenance
    Lets an agent load a design once into a long-lived OpenSTA session and then run static timing and power analysis through dedicated tools or arbitrary Tcl commands. Enables setup/hold slack, TNS/WNS, fmax, DRV, and power queries against the live session.
    9
    MIT
  • A
    license
    C
    quality
    B
    maintenance
    Kiln lets AI agents design, check, slice and print on your own 3D printers (Bambu Lab, Creality, Prusa, Elegoo, Klipper, OctoPrint, USB), with Git-style version history for every design. Open source (AGPL-3.0).
    500
    236
    AGPL 3.0
  • A
    license
    Not graded
    quality
    C
    maintenance
    Enables local AI coding assistants to operate remote Linux EDA clusters over persistent SSH/SCP for digital IC design, simulation, formal property verification, UVM testbench generation, static linting, and Git-backed workspace synchronization.
    MIT
  • A
    license
    Not graded
    quality
    B
    maintenance
    Enables AI agents to design RF filters and SMPS-EMC from spec using three MCP servers that drive LTspice, Qucs-S, and scikit-rf, with closed-form synthesis, real-component optimization, and CISPR-aware compliance checking.
    4
    AGPL 3.0
  • F
    license
    Not graded
    quality
    B
    maintenance
    A terminal emulator MCP server specifically engineered for LLMs with block-oriented design that organizes command input/output into recognizable blocks and semantic session management. Enables AI to efficiently use terminals for writing code, installing software, and executing commands without context overflow.
    1
    -
  • F
    license
    Not graded
    quality
    A
    maintenance
    Enables AI agents such as Claude Code, Cursor, and Codex to safely drive a locally installed Xilinx Vivado through 32 MCP tools spanning GUI/Tcl/attach sessions, synthesis, implementation, timing and CDC analysis, XDC/IO validation, IP inspection, VCD waveform queries, and device programming. It adds structured JSON timing evidence with baseline comparison, Chinese-language diagnostics for CRITICAL WARNINGs, environment self-checks, and evidence-driven workflow prompts that gate each FPGA design stage.
    -