Get MCP server status: daemon version, WebSocket port, connection state, connected instances (each with the version of the .eext it runs), and allowed origins. versionMismatch is true when any connected extension runs a different version from the daemon; fix with a .eext reinstall (bump the version first, EasyEDA ignores same-version reinstalls) and/or bridge_restart.

Restart the EasyEDA bridge daemon. Use this only after the bridge-daemon code itself has changed (new tools, fixed handler logic, etc.) and you want the new code loaded without manually killing the process.

DO NOT use this just because the EasyEDA browser extension was reloaded — the extension reconnects to the existing daemon over WebSocket on its own. The daemon doesn't need restarting for that.

SIDE EFFECTS — please be aware before invoking:

• Every other Claude Code session sharing this daemon also loses its connection mid-flight. Any tool call in progress (in any session) will fail with a connection-dropped error.

• The EasyEDA extension's WebSocket drops and reconnects (typically within a second, capped at 15s). Tool calls landing during that window will fail.

• Your own MCP proxy reconnects transparently and re-lists tools, so the next call after this one will Just Work — but the call itself returns before the new daemon is necessarily up.

Returns { ok, pidWas, message } before the daemon exits (~100ms grace for response to flush).

List all connected EasyEDA Pro instances with their current state (project, active document, open tabs). Use this to find the instance_id you need for other tools when multiple instances are connected.

Get all primitives of a specific type on the PCB, with optional filters. Filters by type: component(layer), track/polyline/arc(net,layer), via(net), pad(layer,net), pour/fill(layer,net), region(layer). Component fields: primitiveId, designator, name, layer, x, y, rotation, primitiveLock, addIntoBom. Track fields: primitiveId, net, layer, startX, startY, endX, endY, lineWidth. Via fields: primitiveId, net, x, y, holeDiameter, diameter, viaType. Pad fields: primitiveId, net, layer, padNumber, x, y.

Get one or more PCB primitives by their type and primitive ID(s)

Get all net names in the PCB design

Get all primitives (tracks, pads, vias, etc.) belonging to a specific net

Get the total routed length of a specific net

Get the current PCB design rule configuration (clearance, width, etc.)

Get net-specific design rules

Get all pins/pads of a specific component by its primitive ID. Pin fields: primitiveId, padNumber, net, layer, x, y. Note (upstream EDA bug, pro-api-sdk issue #33): for components placed via the API in the current editing session, padNumber can read back null until the PCB document is closed and reopened.

Run Design Rule Check (DRC) on the PCB. Returns { passed, errors? }. Some EDA Pro builds report only a pass/fail boolean at runtime (upstream pro-api-sdk issue #27); in that case "errors" is absent and a note says per-violation detail is unavailable. Run this (with connectivity checks) before any fabrication export.

Get currently selected primitives in the PCB editor

Create a single track segment (line) between two points on a specified layer and net. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Create a multi-segment polyline track defined by a series of points. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Create a via at the specified position. Warning (upstream EDA bug, pro-api-sdk issue #32): if an internal plane (PLANE layer) has already been generated, a via on a different net created afterwards does NOT get its anti-pad cut. Rebuilding pours does not fix it; DRC reports "Plane Zone to Via". Regenerate the internal plane after placing vias. This is a fabrication risk, so do not ship until that DRC error is clear. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Create an arc track segment on the PCB. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Create a standalone pad on the PCB. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Create a copper pour region on the PCB. Two upstream EDA bugs to note: (1) pours reflow using the design-rule snapshot taken when the document was opened, so rules written via the API do not affect reflow until the PCB document is closed and reopened (pro-api-sdk issue #34); reopen before rebuilding pours after rule changes. (2) Rebuilding a pour does not cut internal-plane anti-pads for different-net vias created after plane generation (issue #32); regenerate the plane instead. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Create a fill region on the PCB. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Create a design rule region (keepout/constraint area) on the PCB. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Move and/or rotate a component. Can also change its layer (flip), lock status, designator, etc. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Modify properties of an existing track segment (line). Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Modify properties of a PCB primitive. Property keys vary by type:

• via: net, x, y, holeDiameter, diameter, viaType

• polyline: net, layer, lineWidth

• arc: net, layer, startX, startY, endX, endY, arcAngle, lineWidth

• pad: x, y, rotation, net, padNumber, layer

• pour: net, layer, pourFillMethod, preserveSilos, pourName, pourPriority, lineWidth

• fill: layer, net, fillMode, lineWidth

• region: layer, ruleType, regionName, lineWidth All types support: primitiveLock Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Delete one or more PCB primitives by type and IDs. Irreversible via this API: there is no undo call. The whole document is snapshotted to the local backup repo first; the response includes the backup SHA for recovery.

Save the PCB document selected by the "document" parameter (the editor switches to it first, then saves the active document).

Highlight a specific net in the PCB editor for visual inspection

Select all primitives of a specific net in the PCB editor

Clear all selection in the PCB editor

Navigate the PCB editor viewport to specific coordinates. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Navigate and zoom the PCB editor viewport to fit a specific region. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Zoom the viewport to fit the entire board outline

Get the primitive at a specific point on the PCB. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Get all primitives within a rectangular region on the PCB. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Get or set the canvas origin offset relative to data origin. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Convert between canvas coordinates and data coordinates. Coordinates are PCB canvas coordinates in mil (1 mil = 0.001 inch), relative to the canvas origin: +X = rightward, +Y = upward. Lengths (widths, diameters) are also in mil. Use pcb_canvas_origin to read/set the origin offset and pcb_convert_coordinates to convert between canvas and data coordinates.

Import changes from schematic into the PCB (sync schematic to PCB). Warning (upstream EDA bug, pro-api-sdk issue #33): pads of components newly placed by this call can read back with a null pad number until the PCB document is reloaded, and DRC may report an unstructured "Netlist Error". Close and reopen the PCB document (or reload via editor_open_document) before reading pads of freshly placed components.

Get all components in the schematic with their properties, positions, rotations, designators, etc. To identify what a component is, check: designator (e.g. "R1", "U3"), name (part name/number), manufacturer, manufacturerId (manufacturer part number), supplier, supplierId (supplier part number, e.g. JLCPCB/LCSC number), and footprint. All fields: primitiveId, componentType, designator, name, x, y, rotation, mirror, addIntoBom, addIntoPcb, footprint, manufacturer, manufacturerId, supplier, supplierId, net, otherProperty. otherProperty contains user-defined custom attributes — contents vary per component. Template expressions like ={Manufacturer Part} are automatically resolved to their actual values.

Get one or more schematic components by primitive ID(s)

Get all pins of a schematic component by its primitive ID. Pin fields: primitiveId, pinNumber, name, net, x, y, rotation. Each pin includes a net field with the net name it is connected to (empty string if unconnected). Pins connected to $-prefixed nets (like $R11_1) are on unnamed nets that still carry real signals — use sch_get_connectivity with that net name to see what else is connected.

Get all wires in the schematic, optionally filtered by net name

Get one or more wires by primitive ID(s)

Get all currently selected primitives in the schematic editor

Get primitive IDs of all currently selected primitives in the schematic editor

Get a schematic primitive by its ID with all properties

Get the type of a schematic primitive by its ID

Get the bounding box of one or more schematic primitives

Get the raw schematic netlist in the specified format. WARNING: The JLCEDA format response is very large (100KB+). Prefer sch_get_connectivity for connectivity questions — it returns the same net/pin data in a much more compact format with resolved part names. Only use this tool when you need a specific netlist export format (Allegro, PADS, etc.) or the full raw netlist data.

Export the schematic-side BOM as parsed rows (one object per BOM line, keyed by column header). The schematic BOM is the source of truth for supplier metadata — recommended for verifying BOM integrity after batch edits (e.g. confirm Supplier Part / LCSC numbers survived a sch_modify_component run). Columns follow the EasyEDA BOM template, e.g. "Designator", "Quantity", "Manufacturer Part", "Supplier Part". Supports filter/fields/limit on the rows (e.g. filter: {"Designator": "R*"}). For a PCB-side BOM file (xlsx/csv, base64), use pcb_export with format:"bom" instead.

Get compact connectivity data: which nets connect which component pins, with resolved part names. Much smaller than sch_get_netlist — use this for connectivity questions. Returns nets (net → pin connections like "U3.2(GND)") and components (designator → part + pin assignments). Auto-generated net names (starting with $) are hidden from the nets section but still appear in component pin assignments. IMPORTANT: $-prefixed nets (like $R11_1, $U3_7) represent real electrical connections — they are unnamed nets where the designer didn't assign a net label. When investigating a component's full circuit context, you MUST look at $-prefixed nets in its pin assignments and trace them to see what else is connected. These often carry critical signals (reset lines, boot pins, enable pins) that would otherwise be invisible. Use the depth parameter (default 2) to automatically trace through $-prefixed nets and discover indirect connections — so by default, you already see one hop through unnamed nets (pull-ups, series resistors, boot/reset circuitry). Pass depth=1 to see only direct connections, or 3–5 to chase longer chains. The response includes a note field reminding you of the depth used.

Run Design Rule Check (DRC) on the schematic. Returns { passed, errors? }. Some EDA Pro builds report only a pass/fail boolean at runtime (upstream pro-api-sdk issue #27); in that case "errors" is absent and a note says per-violation detail is unavailable.

Create a schematic component from a library device reference. Use lib_search_device or lib_get_device_by_lcsc first to get the component object. IMPORTANT: The component object must include uuid, symbolUuid, footprintUuid, AND libraryUuid — passing only {deviceUuid, libraryUuid} will fail with a validation error. Pass the full object returned by lib_get_device_by_lcsc with libraryUuid added (from lib_get_system_library_uuid).

Create one or more Power/Ground/AnalogGround/ProtectGround net flags in the schematic. Pass individual parameters for a single flag, or use "batch" array for multiple flags in one call.

Create one or more IN/OUT/BI directional net ports in the schematic. Pass individual parameters for a single port, or use "batch" array for multiple ports in one call.

Delete one or more schematic components by their primitive IDs. Irreversible via this API: there is no undo call. The whole document is snapshotted to the local backup repo first; the response includes the backup SHA for recovery.

Modify properties of a schematic component (position, rotation, designator, etc.). Metadata is preserved automatically (bug-1 fix, this fork only): fields you do not pass (supplierId, otherProperty, manufacturer, manufacturerId, supplier, uniqueId) are snapshotted before the write and merged back, so a position-only edit no longer wipes the BOM row. Passing an explicit value (including null) still applies it. Stock EasyEDA does NOT do this — its modify() re-serialises from the property argument alone. LIMITATION: the "document" parameter cannot move a component between schematic pages. Passing a different page's UUID switches the editor but the underlying call fails (undefined.getState_ComponentType); cross-page moves still require a manual UI Cut, switch page, Paste.

Bulk-swap supplier metadata on schematic components matching a filter. WARNING (field-confirmed): this swaps supplier METADATA only. The canvas symbol and its label stay those of the OLD part. Use this ONLY when the replacement is a true drop-in with identical schematic symbol and PCB footprint (e.g. same 100nF 0603 cap in a different reel). For any part with a different symbol, footprint, or pin count, delete the component and re-add it instead — otherwise the schematic and BOM will disagree with the canvas symbol/label. Uses the same bug-1 metadata guard as sch_modify_component: unspecified fields (otherProperty, uniqueId, position, symbol, etc.) are preserved via a snapshot-and-merge round trip, so a swap that only touches supplierId doesn't wipe the rest of the BOM row. Non-dry-run swaps snapshot first: the active document (or, with allSchematicPages, the whole project) is committed to the local backup repo before any write, and the response includes the backup SHA. Note the multi-page walk is not atomic — if a page fails to open mid-walk the swap aborts with earlier pages already written; use the backup SHA to recover. Typical uses: rotate to a cheaper LCSC alt (match: {supplierId: "C25804"}, replace: {supplierId: "C17414", manufacturerId: "..."}), or bulk-tag a designator prefix (match: {designator: "R*"}, replace: {manufacturer: "YAGEO"}). match: filter fields with the same semantics as read-tool filter — exact string, ["a","b"] OR-array, or "prefix*" glob. Any component field is accepted (designator, supplierId, manufacturerId, manufacturer, ...). Matching runs against RESOLVED values: fields stored as ={...} template expressions are resolved from the netlist before the filter applies, matching what sch_get_all_components shows. If the netlist cannot be fetched, matching falls back to raw stored values. replace: at least one of supplierId, manufacturerId, manufacturer, supplier. dryRun: if true, returns the matches with before/after but does NOT modify (and takes no backup). Recommended for the first pass. allSchematicPages: walk every schematic page instead of only the active one; original page is restored. Returns { dryRun, swappedCount, swapped:[{primitiveId, designator, page, before, after}], backup? }. Always re-run sch_export_bom afterward to confirm BOM integrity.

Create a wire in the schematic defined by a series of coordinate points

Delete one or more wires by their primitive IDs. Irreversible via this API: there is no undo call. The whole document is snapshotted to the local backup repo first; the response includes the backup SHA for recovery.

Modify properties of an existing wire

Select and highlight primitives in the schematic editor by designators, pins, or nets. Selection is additive — each call adds to the current selection. There is currently no programmatic way to clear the selection; the user must click on empty space in the editor to deselect. Pin format: "U1_1" (designator_pinNumber). Components selects the whole component, pins highlights just the pin, nets highlights the entire wire/net.

Update the schematic netlist

Save the current schematic document

Import changes from PCB back into the schematic

Search the component library for devices by keyword. Returns a list of matching components with their UUIDs, names, descriptions, and package info.

Get detailed information about a specific device by its UUID, including symbol, footprint, and all properties

Get device(s) by LCSC C-number(s). Useful for finding specific components like "C17414" for a 2.2k resistor.

Get the UUID of the system (built-in) component library

Get a list of all available component libraries with their UUIDs and names

Get the UUID of the user's personal library (returns undefined on private deployments)

Get the UUID of the current project's library (returns undefined if no project is open)

Get a library symbol's metadata (name, classification, description) by UUID. Does NOT return the .esym source — use lib_symbol_open_in_editor + document_get_source for that.

Copy a library symbol from one library to another (e.g. system → personal). Returns the new symbol UUID. Fails if newSymbolName collides in the target library.

Delete a library symbol. IRREVERSIBLE: no undo, and no backup snapshot is taken (library assets are not documents). Fetch and save the symbol source with lib_symbol_get first if you may need to restore it. Returns boolean success.

Open a library symbol in the EasyEDA editor as a tab. Returns the new tabId — use that as the document UUID for document_get_source. Only symbols in a personal, team or project library can be opened; EDA Pro refuses system-library symbols (the call errors rather than returning a tabId), so lib_symbol_copy one into your own library first.

Replace a library symbol's entire .esym source. IRREVERSIBLE: no undo, and no backup snapshot is taken (library assets are not documents). Fetch and save the current source with lib_symbol_get first if you may need to restore it. The symbol must live in a library you can write to (personal/team/project). Returns boolean success.

Get a library footprint's metadata (uuid, library, name, classification, description) by UUID. Read the source itself by opening the footprint with lib_footprint_open_in_editor and calling document_get_source on the returned tabId.

Open a library footprint in the EasyEDA editor as a tab. Returns the new tabId: use it as the document UUID for document_get_source / document_save_to_file. Only footprints in a personal, team or project library can be opened (system-library ones are refused).

Replace a library footprint's entire source. IRREVERSIBLE: no undo, and no backup snapshot is taken (library assets are not documents). Read and save the current source first (lib_footprint_open_in_editor + document_save_to_file). The footprint must live in a library you can write to (personal/team/project). Returns boolean success.

Copy a library device from one library to another. Returns the new device UUID. Whether the device's symbol/footprint are deep-copied or referenced cross-library is yet to be confirmed empirically.

Modify a library device — re-bind its symbol/footprint, or change name/classification/description/properties. Pass only the fields you want to change. Pass null to clear an optional field. Use the association arg to swap to a different symbol or footprint UUID.

Delete a library device. Does NOT delete its referenced symbol/footprint. IRREVERSIBLE: no undo, and no backup snapshot is taken (library assets are not documents). Record the device data with lib_get_device first if you may need to restore it. Returns boolean success.

Export the PCB design in various formats. Returns { fileName, data (Base64), size }.

BEFORE generating any fabrication output (gerber, odbplus, drill, pick_and_place): run pcb_run_drc (and sch_run_drc) and resolve all violations. Clearance DRC alone is not sufficient — this fork exists partly because API-drawn tracks passed clearance DRC while being electrically dead to their SMD pads; only a No-Connection/connectivity check surfaced it. Include connectivity checks in the DRC run before shipping.

Formats: dsn (for FreeRouting), gerber (manufacturing), bom (bill of materials), pick_and_place (assembly), 3d (STEP/OBJ), pdf, netlist, dxf, altium, pads, odbplus (ODB++ archive with stackup+nets), ipc_d_356 (netlist test format), flying_probe, test_point, autoroute_json, autolayout_json. Use fileType for sub-formats: "xlsx"/"csv" (bom, pick_and_place, test_point), "step"/"obj" (3d).

WARNING: response is Base64 in the MCP reply — for large outputs (gerber zips, 3d STEP) prefer pcb_export_to_file which writes straight to disk.

Most formats accept extra options forwarded as-is to the underlying EasyEDA getXxxFile call. Common ones (unit values are the literal strings "mm" / "inch" / "mil"): gerber: { unit: "mm" | "inch", colorSilkscreen, digitalFormat: {integerNumber, decimalNumber}, other: {metallicDrillingInformation, nonMetallicDrillingInformation, drillTable, flyingProbeTestingFile}, layers: [{layerId, isMirror}], objects: [...] } odbplus: { unit: "inch", otherData: {metallizedDrilledHoles, nonMetallizedDrilledHoles, drillTable, flyingProbeTestFile}, layers: [{layerId, mirror}], objects: [{objectName}] } pick_and_place:{ unit: "mm" | "mil" } 3d: { element: [...], modelMode: "Outfit" | "Parts", autoGenerateModels } bom: { template, filterOptions, statistics, property, columns } dxf: { layers: [{layerId, mirror}], objects: [...] } Omit options to get sensible defaults. For gerber and odbplus, omitting layers exports all enabled copper (Top, Bottom, and any Inner1..InnerN that are enabled) plus the standard silk/mask/paste/outline aux layers — unlike EasyEDA's raw default which silently drops inner copper even on 4L+ boards.

CAUTION: options keys cannot override the top-level document/instance_id routing fields — those always take precedence to prevent accidental cross-document export.

Export the PCB design in various formats directly to a local file path — preferred over pcb_export when the output is large (gerber/odbplus zips, 3d STEP, pdf), since it avoids shipping the bytes back through the MCP response as Base64.

BEFORE generating any fabrication output: run pcb_run_drc (and sch_run_drc) and resolve all violations. Clearance DRC alone is not sufficient — include connectivity/No-Connection checks; see pcb_export for why.

Returns { saved: path, size, originalName, format }.

Formats: same as pcb_export. See pcb_export for option shapes.

Most formats accept extra options forwarded as-is to the underlying EasyEDA getXxxFile call. Common ones (unit values are the literal strings "mm" / "inch" / "mil"): gerber: { unit: "mm" | "inch", colorSilkscreen, digitalFormat: {integerNumber, decimalNumber}, other: {metallicDrillingInformation, nonMetallicDrillingInformation, drillTable, flyingProbeTestingFile}, layers: [{layerId, isMirror}], objects: [...] } odbplus: { unit: "inch", otherData: {metallizedDrilledHoles, nonMetallizedDrilledHoles, drillTable, flyingProbeTestFile}, layers: [{layerId, mirror}], objects: [{objectName}] } pick_and_place:{ unit: "mm" | "mil" } 3d: { element: [...], modelMode: "Outfit" | "Parts", autoGenerateModels } bom: { template, filterOptions, statistics, property, columns } dxf: { layers: [{layerId, mirror}], objects: [...] } Omit options to get sensible defaults. For gerber and odbplus, omitting layers exports all enabled copper (Top, Bottom, and any Inner1..InnerN that are enabled) plus the standard silk/mask/paste/outline aux layers — unlike EasyEDA's raw default which silently drops inner copper even on 4L+ boards.

CAUTION: options keys cannot override the top-level document/instance_id routing fields — those always take precedence to prevent accidental cross-document export.

Import routing or layout result files into the PCB (Base64-encoded). Formats: autoroute_json (JSON autoroute), autolayout_json (JSON autolayout), autoroute_ses (FreeRouting SES).

Manage DRC rule configurations. Actions:

• get_current_name: get current active config name

• get_by_name: get config by name (configurationName)

• get_all: get all configs (includeSystem optional)

• save: save config (ruleConfiguration, configurationName; allowOverwrite optional)

• rename: rename config (originalName, newName)

• delete: delete config (configurationName)

• get_default_name: get default config name

• set_default: set as default (configurationName) Warning (upstream EDA bug, pro-api-sdk issue #34): saved rule changes read back correctly but do NOT affect pour reflow until the PCB document is closed and reopened. Reopen the document before rebuilding pours.

Manage net-specific design rules. Actions:

• overwrite_net: overwrite net rules (netRules: array of net rule objects)

• get_net_by_net: get net-by-net clearance rules

• overwrite_net_by_net: overwrite net-by-net rules (netByNetRules: object)

• get_region: get region-specific rules

• overwrite_region: overwrite region rules (regionRules: array of region rule objects) Warning (upstream EDA bug, pro-api-sdk issue #34): overwritten rules read back correctly but do NOT affect pour reflow until the PCB document is closed and reopened. Reopen the document before rebuilding pours.

Manage net classes. Actions:

• get_all: get all net class definitions

• create: create net class (netClassName, nets: string[]; color optional)

• delete: delete net class (netClassName)

• rename: rename net class (originalName, newName)

• add_net: add net(s) to class (netClassName, net: string|string[])

• remove_net: remove net(s) from class (netClassName, net: string|string[])

Manage differential pair definitions. Actions:

• get_all: get all differential pairs

• create: create diff pair (name, positiveNet, negativeNet)

• delete: delete diff pair (name)

• rename: rename diff pair (originalName, newName)

• modify_nets: modify positive/negative net (name, positiveNet and/or negativeNet)

Manage equal-length net groups. Actions:

• get_all: get all equal-length groups

• create: create group (name, nets: string[]; color optional)

• delete: delete group (name)

• rename: rename group (originalName, newName)

• add_net: add net(s) to group (name, net: string|string[])

• remove_net: remove net(s) from group (name, net: string|string[])

Manage pad pair groups for length-matching. Actions:

• create: create group (name, padPairs: [[padId1, padId2], ...])

• delete: delete group (name)

• rename: rename group (originalName, newName)

Manage PCB layers. Actions:

• get_all: get all layers with properties

• select: set active layer (layer: string)

• set_visible: show layer(s) (layer optional; setOtherLayerInvisible optional for solo mode)

• set_invisible: hide layer(s) (layer optional; setOtherLayerVisible optional)

• lock: lock layer(s) (layer optional)

• unlock: unlock layer(s) (layer optional)

• set_copper_count: set copper layers (count: 2,4,6,...,32). WARNING: REDUCING the count permanently discards all copper (tracks, pours, vias' inner connections) on the removed inner layers. No undo, and no backup snapshot is taken. Export the board first (pcb_export_to_file or document_save_to_file) if the layers being removed hold routing.

• modify: modify layer properties (layer: string, property: {name?, type?, color?, transparency?})

• add_custom: add a new custom layer

• remove: remove a custom layer (layer: string). WARNING: deletes the layer AND everything drawn on it. No undo, no backup snapshot. Export first if in doubt.

Get the current project structure: boards (with their schematics/PCBs), standalone schematics with pages, standalone PCBs, and panels. Also shows which document is currently focused.

Get detailed info about the currently focused document. For schematic pages, includes parent schematic info. For PCBs, includes associated board info.

Open/navigate to a specific document by UUID. Works for schematic page UUIDs, PCB UUIDs, and panel UUIDs.

Get all currently open tabs in the editor, with the active tab marked. Also returns the split screen structure.

Get the raw source code of the currently active document (schematic page, PCB, or panel). Returns the document as a string in EasyEDA's internal format (newline-delimited JSON arrays). Use editor_open_document to switch to the desired document first, then call this tool. The source can be modified and written back with document_set_source.

For schematic documents, the source is also run through the schema validator as a side effect — any unknown tags get logged to ~/.easyeda-schema-discovery.jsonl so we can grow the schema. The response itself is unchanged. Use document_validate for a structured validation report.

FAST-BATCH WORKFLOW: for making many changes at once, it is much faster to export the document or project (document_save_to_file / project_export_file), edit the raw source on disk, then re-upload (document_load_from_file / project_import_file) than to issue many small per-primitive MCP calls. The document source is newline-delimited JSON arrays; .epro files are ZIP archives of the same. Every destructive upload is auto-backed-up to a local git repo first — the response includes a backup SHA you can use to find the prior state if the edit goes wrong. Upload tools accept validate='off'|'warn'|'strict' (default 'strict') which runs the Zod schema on the new source — see document_validate for standalone validation.

Replace the source code of the currently active document. Accepts the full document source as a string (same format returned by document_get_source). Returns { success, backup: { sha, path }, validation: {...} } on success, or throws if validation aborts the upload or the pre-edit backup could not be written. WARNING: This replaces the entire document. Always get the current source first, modify it, then set it back. A backup of the prior state is taken automatically before the replacement (after validation passes) and committed to a local git-tracked repo — the returned backup.sha references the pre-edit state. Validation runs only for schematic documents (documentType=1); other types skip with a status.

FAST-BATCH WORKFLOW: for making many changes at once, it is much faster to export the document or project (document_save_to_file / project_export_file), edit the raw source on disk, then re-upload (document_load_from_file / project_import_file) than to issue many small per-primitive MCP calls. The document source is newline-delimited JSON arrays; .epro files are ZIP archives of the same. Every destructive upload is auto-backed-up to a local git repo first — the response includes a backup SHA you can use to find the prior state if the edit goes wrong. Upload tools accept validate='off'|'warn'|'strict' (default 'strict') which runs the Zod schema on the new source — see document_validate for standalone validation.

Save the source code of the currently active document to a local file. Fetches the document source from EasyEDA and writes it directly to disk. The file will contain the document in EasyEDA's internal format (newline-delimited JSON arrays). Use document_load_from_file to push a modified file back.

For schematic documents, the source is also run through the schema validator in warn mode — the returned JSON includes a validation report, and any unknown tags are logged to ~/.easyeda-schema-discovery.jsonl. Since this is a download (EasyEDA's output), a schema mismatch means our schema is missing coverage, not that the data is bad.

FAST-BATCH WORKFLOW: for making many changes at once, it is much faster to export the document or project (document_save_to_file / project_export_file), edit the raw source on disk, then re-upload (document_load_from_file / project_import_file) than to issue many small per-primitive MCP calls. The document source is newline-delimited JSON arrays; .epro files are ZIP archives of the same. Every destructive upload is auto-backed-up to a local git repo first — the response includes a backup SHA you can use to find the prior state if the edit goes wrong. Upload tools accept validate='off'|'warn'|'strict' (default 'strict') which runs the Zod schema on the new source — see document_validate for standalone validation.

Load document source from a local file and push it into the currently active document. Reads the file from disk and calls setDocumentSource to replace the document contents. The file must contain valid EasyEDA document source (same format as document_get_source / document_save_to_file). WARNING: This replaces the entire document. A backup of the prior state is taken automatically (after validation passes) and committed to a local git-tracked repo — the returned backup.sha references the pre-edit state. Validation runs only for schematic documents (documentType=1); other types skip with a status.

FAST-BATCH WORKFLOW: for making many changes at once, it is much faster to export the document or project (document_save_to_file / project_export_file), edit the raw source on disk, then re-upload (document_load_from_file / project_import_file) than to issue many small per-primitive MCP calls. The document source is newline-delimited JSON arrays; .epro files are ZIP archives of the same. Every destructive upload is auto-backed-up to a local git repo first — the response includes a backup SHA you can use to find the prior state if the edit goes wrong. Upload tools accept validate='off'|'warn'|'strict' (default 'strict') which runs the Zod schema on the new source — see document_validate for standalone validation.

Export the entire current project as a .epro file (ZIP archive) saved directly to a local path. The .epro file contains: project.json (manifest with board/schematic/PCB associations), SHEET/ (schematics), PCB/ (layouts), SYMBOL/ (component symbols), FOOTPRINT/ (footprints), INSTANCE/ (per-instance attribute overrides), and more. All internal files are human-readable newline-delimited JSON arrays.

FAST-BATCH WORKFLOW: for making many changes at once, it is much faster to export the document or project (document_save_to_file / project_export_file), edit the raw source on disk, then re-upload (document_load_from_file / project_import_file) than to issue many small per-primitive MCP calls. The document source is newline-delimited JSON arrays; .epro files are ZIP archives of the same. Every destructive upload is auto-backed-up to a local git repo first — the response includes a backup SHA you can use to find the prior state if the edit goes wrong. Upload tools accept validate='off'|'warn'|'strict' (default 'strict') which runs the Zod schema on the new source — see document_validate for standalone validation.

Import a project file (.epro) from a local path into EasyEDA Pro. Can import into an existing project (replacing its contents) or create a new project. A new project is saved to the same team/workspace as the project open in the target window (on the desktop client, the local projects folder); open any project there first. Supports EasyEDA Pro, Altium, KiCad, EAGLE, PADS, and LTspice formats. When importing into an existing project (existingProjectUuid set), a backup of the prior project state is taken automatically and committed to a local git-tracked repo — the returned backup.sha references the pre-import state.

FAST-BATCH WORKFLOW: for making many changes at once, it is much faster to export the document or project (document_save_to_file / project_export_file), edit the raw source on disk, then re-upload (document_load_from_file / project_import_file) than to issue many small per-primitive MCP calls. The document source is newline-delimited JSON arrays; .epro files are ZIP archives of the same. Every destructive upload is auto-backed-up to a local git repo first — the response includes a backup SHA you can use to find the prior state if the edit goes wrong. Upload tools accept validate='off'|'warn'|'strict' (default 'strict') which runs the Zod schema on the new source — see document_validate for standalone validation.

Validate a document's source against the Zod-backed EasyEDA schema. Runs on the currently active document by default, or on a local file if filePath is provided. Schematic (.esch, documentType=1) and PCB (.epcb, documentType=3) documents are validated; other types return a "skipped" report with a reason. Unknown tags (shapes the schema doesn't cover yet) are appended to the discovery log at ~/.easyeda-schema-discovery.jsonl (override via EDA_DISCOVERY_LOG).

Returns a JSON-serializable report: { docType, lineCount, knownCount, unknownTagCount, invalidCount, samples: { unknownTags, invalid } }. Known issues are samples of known tags whose shape failed validation (typically writer bugs); unknowns are tags not yet in the schema vocabulary.