check_constant_time
Check if a Verilog module's completion signal is independent of secret inputs. Returns CONSTANT_TIME or LEAKY, listing which secrets influence the completion signal.
Instructions
Decide whether a Verilog module's completion signal is independent of declared secret inputs. Returns CONSTANT_TIME or LEAKY, and on LEAKY names the secrets that reach the completion signal. You cannot declare a design constant-time yourself: re-run this tool after any fix.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| module | No | module name, if several | |
| secrets | Yes | input names carrying sensitive values; never inferred | |
| verilog | Yes | Verilog-2001 source | |
| observation | No | completion signal name (default 'done') |