verilog_compile_check

Does the description disclose side effects, auth requirements, rate limits, or destructive behavior?

With no annotations provided, the description carries the full transparency burden. It discloses that the tool returns SKIP with installation guidance when iverilog/verilator are missing, returns SKIP for VHDL files with alternative guidance, and notes that iverilog -t null produces no artifacts. It also documents both tool modes and timeout behavior.

Agents need to know what a tool does to the world before calling it. Descriptions should go beyond structured annotations to explain consequences.

Is the description appropriately sized, front-loaded, and free of redundancy?

The description is well-organized and front-loaded, starting with purpose and typical use, then covering installation, modes, and parameters. Every section serves a purpose and no content is filler; the length is justified by the tool's complexity.

Shorter descriptions cost fewer tokens and are easier for agents to parse. Every sentence should earn its place.

Given the tool's complexity, does the description cover enough for an agent to succeed on first attempt?

Given the tool's moderate complexity, the presence of an output schema, and the fact that this description lacks annotations, it is remarkably complete. It covers input requirements, tool selection, timeout, unsupported files, and failure modes, leaving no critical ambiguity for an agent.

Complex tools with many parameters or behaviors need more documentation. Simple tools need less. This dimension scales expectations accordingly.

Does the description clarify parameter syntax, constraints, interactions, or defaults beyond what the schema provides?

The schema has 0% description coverage, so the description fully compensates by explaining every parameter: files accepts .v/.sv and rejects .vhd/.vhdl with a SKIP, tool supports auto/iverilog/verilator with default auto, and timeout is subprocess timeout defaulting to 30. This adds substantial meaning beyond the bare schema.

Input schemas describe structure but not intent. Descriptions should explain non-obvious parameter relationships and valid value ranges.

Does the description clearly state what the tool does and how it differs from similar tools?

The description clearly states the tool performs Verilog syntax and connectivity checks using iverilog/verilator, and positions it as a fast alternative to Vivado synthesis. This is a specific verb+resource combination that distinguishes it from synthesis-related sibling tools.

Agents choose between tools based on descriptions. A clear purpose with a specific verb and resource helps agents select the right tool.

Does the description explain when to use this tool, when not to, or what alternatives exist?

It explicitly indicates when to use the tool (after writing/modifying RTL, for quick verification before synthesis) and when not to use it (for .vhd/.vhdl files, where it returns SKIP and recommends check_syntax). It also explains behavior when tools are not installed, providing clear context for invocation.

Agents often have multiple tools that could apply. Explicit usage guidance like "use X instead of Y when Z" prevents misuse.