watch_signal
Automatically stops simulation when a RTL signal matches a specified condition, enabling efficient debugging without manual probing.
Instructions
Set a watchpoint to stop simulation when a signal matches a condition.
The simulation will automatically stop at the exact clock edge where the condition becomes true. Much more efficient than manual probing.
Args: signal: Full hierarchical signal path (e.g. "top.dut.r_state[3:0]"). op: Comparison operator ("==", "!=", ">", "<", ">=", "<="). value: Target value in Verilog format (e.g. "8'h10", "4'b1010").
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| signal | Yes | ||
| op | No | == | |
| value | No |
Output Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |
Implementation Reference
- src/xcelium_mcp/server.py:409-422 (handler)The watch_signal function executes the tool logic by setting a watchpoint via the bridge.
async def watch_signal(signal: str, op: str = "==", value: str = "") -> str: """Set a watchpoint to stop simulation when a signal matches a condition. The simulation will automatically stop at the exact clock edge where the condition becomes true. Much more efficient than manual probing. Args: signal: Full hierarchical signal path (e.g. "top.dut.r_state[3:0]"). op: Comparison operator ("==", "!=", ">", "<", ">=", "<="). value: Target value in Verilog format (e.g. "8'h10", "4'b1010"). """ bridge = _get_bridge() result = await bridge.execute(f"__WATCH__ {signal} {op} {value}") return f"Watchpoint set: {result}" - src/xcelium_mcp/server.py:408-408 (registration)The watch_signal tool is registered using the @mcp.tool() decorator.
@mcp.tool()