watch_signal
Automatically stops simulation when a RTL signal matches a specified condition, enabling efficient debugging without manual probing.
Instructions
Set a watchpoint to stop simulation when a signal matches a condition.
The simulation will automatically stop at the exact clock edge where the condition becomes true. Much more efficient than manual probing.
Args: signal: Full hierarchical signal path (e.g. "top.dut.r_state[3:0]"). op: Comparison operator ("==", "!=", ">", "<", ">=", "<="). value: Target value in Verilog format (e.g. "8'h10", "4'b1010").
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| signal | Yes | ||
| op | No | == | |
| value | No |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |