cst_pcb_via_fence
Generate rows of vias along a path to create isolation barriers or Substrate Integrated Waveguides (SIW) in PCB designs.
Instructions
Create a row (or multiple rows) of vias along a path for isolation or Substrate Integrated Waveguide (SIW) construction. Generates an array of cylinders from start to end point with specified spacing.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| name | Yes | Base name for the via fence | |
| rows | No | Number of parallel rows (1-3) | |
| x_end | Yes | X coordinate of the fence end in mm | |
| y_end | Yes | Y coordinate of the fence end in mm | |
| x_start | Yes | X coordinate of the fence start in mm | |
| y_start | Yes | Y coordinate of the fence start in mm | |
| component | No | CST component name | PCB |
| row_offset_mm | No | Lateral offset between rows for staggering in mm | |
| via_spacing_mm | Yes | Center-to-center spacing between vias in mm | |
| pad_diameter_mm | Yes | Via pad diameter in mm | |
| via_diameter_mm | Yes | Via drill diameter in mm |