Verify (ERC/DRC/review)
verifyRun KiCad ERC, DRC, and design review checks to surface actionable findings, compare new versus fixed issues, and get the exact next tool call before fabrication.
Instructions
Run KiCad's own checks and get actionable findings. Use after EVERY batch of edits (sch_apply, pcb_*), and before fab_export.
what: list of 'erc' (schematic electrical rules), 'drc' (board rules + unrouted nets + schematic↔board parity; zones are refilled in memory,
the file is not modified) and 'review' (engineering heuristics, see design_review). Default: ['erc'] plus 'drc' when a board exists.
Each finding has severity, type, message, refs (pins like 'U1.3' / footprints), at [x,y] mm (on sheet for sub-sheets) and fix = the exact
next tool call, already pointed at the right sub-sheet. Repeats of one problem are merged into one entry with count + all refs.
next is the single most useful call to make now; new / fixed compare with the previous run. Checks run on the SAVED files.
Example: verify(what=['erc','drc'])
Tool call template
This tool declares no required parameters. Add optional parameters from the input schema as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {},
"name": "verify"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| what | No | ||
| limit | No | max finding entries returned per check (default 25) | |
| parity | No | check schematic↔board parity in DRC (default true) | |
| refill | No | refill zones before DRC (default true) | |
| project | No | project path (default: active) |