to_sva
Converts an assume-guarantee LTL contract into a SystemVerilog checker module with assume/assert properties, reset handling, and optional bind statements for design integration.
Instructions
Write a contract as a SystemVerilog checker module: assumptions as
assume property, guarantees as assert property, clocked by
@(edge clock); a formula G p is checked at every cycle, any other once
(initial). reset (e.g. "rst" or "!rst_n") disables the properties
while it holds; bind, the name of a design module, adds a bind
statement (ports connected by name; names, from parse_sva, connects
the hierarchical names). Any tool that reads SVA can check the module.
Real variables cannot be written.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"contract": "<contract>"
},
"name": "to_sva"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| bind | No | ||
| edge | No | posedge | |
| clock | No | clk | |
| names | No | ||
| reset | No | ||
| module | No | ||
| contract | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |