rtl_ports
Reads Verilog/SystemVerilog module ports as state-machine contract variables, exposing inputs, outputs, types, reset, and the start step for formal checks.
Instructions
The ports of a Verilog or SystemVerilog module read as a state machine:
the inputs and the outputs with their types ("bool", "word[n]"), as the
variables of a contract checked against it, the reset (not an input when
given), and start, the step from which the contracts are checked.
Tool call template
Replace each placeholder with a value matching the input schema. Only required parameters are included; add optional parameters as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {
"rtl": "<rtl>"
},
"name": "rtl_ports"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| rtl | Yes |