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CadenceAI MCP

CadenceAI MCP

by chaosAIman

CadenceAI MCP — Cadence EDA Tools for AI Assistants

License: MIT Python 3.10+ MCP Tools

A Model Context Protocol (MCP) server that exposes Cadence EDA tools (OrCAD Capture, Allegro PCB Designer, PSpice) to AI assistants like Claude, Cursor, and Cline — letting them browse PCBs, generate schematics, and run circuit simulations through a single, license-free, cross-platform interface.


✨ Features

Domain

What AI can do

Environment

Auto-detect SPB installation, license status, available batch commands

PCB files

Find .brd files, parse text assets from the Allegro binary DB

Batch CLI

Invoke 60+ safe allegro_batch subcommands (artwork, netin, dump_libraries…)

Schematics

Generate SPICE netlists, .DSN project XML, Allegro physical netlists

Simulation

Generate circuits from templates, run via PSpice / ngspice / analytical fallback

Netlist flow

DSL → SPICE → Allegro tel-format in one end-to-end pipeline

13 MCP tools, 75+ Allegro batch subcommands wrapped with safety allow-list, 6 circuit templates, all available out of the box.


Related MCP server: KiCAD MCP Server

🚀 Quick Start

1. Install

git clone https://github.com/cadenceai/cadence-mcp.git
cd cadence-mcp
pip install -e .

2. Probe your environment

python -m cadence_mcp.server --probe
{
  "cds_root": "C:\\Cadence\\SPB_23.1",
  "allegro_batch": "C:\\Cadence\\SPB_23.1\\tools\\bin\\allegro_batch.exe",
  "pspice_exe": "C:\\Cadence\\SPB_23.1\\tools\\bin\\pspice.exe",
  "license_present": false,
  "batch_commands_count": 75,
  ...
}

3. Register in your MCP client (e.g. Cursor / Claude Desktop)

Edit ~/.cursor/mcp.json:

{
  "mcpServers": {
    "cadence": {
      "command": "python",
      "args": ["-m", "cadence_mcp.server"],
      "cwd": "D:\\AIBench\\CadenceAI"
    }
  }
}

Restart the client. AI now has 13 Cadence tools at its disposal.


🛠 The 13 Tools

Environment & Diagnostics

Tool

Purpose

cadence_probe

Detect SPB install, license, batch commands

cadence_env_vars

Dump CDSROOT / CDS_LIC_FILE / LM_LICENSE_FILE

allegro_batch_commands

List all available Allegro batch subcommands

safe_batch_commands

List the 56 commands safe to invoke

PCB Design

Tool

Purpose

find_brd_files

Recursively find .brd files with metadata

parse_brd_file

Extract readable strings from binary .brd

allegro_batch_run

Run one batch subcommand (timeout + allow-list)

Schematic & Netlist

Tool

Purpose

generate_spice_netlist

From template or DSL → SPICE netlist file

parse_circuit_dsl

Decompose DSL into components / directives

generate_schematic_dsn

OrCAD Capture-compatible .DSN XML

netlist_to_allegro

SPICE → Allegro tel physical netlist

Simulation

Tool

Purpose

list_simulation_templates

Enumerate 6 circuit templates (RC, RLC, diode, ...)

run_circuit_simulation

Auto-route to PSpice / ngspice + extract measurements


📐 Architecture

                  ┌──────────────────────────┐
   AI Client ───► │  MCP Server (stdio)      │
  (Claude /       │   13 tools               │
   Cursor)        │                          │
                  └────────────┬─────────────┘
                               │
       ┌───────────────────────┼─────────────────────────┐
       │                       │                         │
       ▼                       ▼                         ▼
 ┌──────────────┐      ┌──────────────────┐      ┌──────────────┐
 │ env_detect   │      │ simulator        │      │ schematic    │
 │ pcb.py       │      │   (PySpice/PSpice)│      │ pcb.py       │
 │  (read-only) │      │                  │      │  (text gen)  │
 └──────────────┘      └──────────────────┘      └──────────────┘
       │                       │                         │
       ▼                       ▼                         ▼
   Allegro .brd            PSpice / ngspice           Allegro netin
   files / dirs            binary backend             physical netlist

Three independent modules + one MCP server bootstrap. No monolithic controller, no hidden state beyond an env cache.


🧪 Testing

python tests/test_all.py

Covers 10 scenarios end-to-end:

TEST  1: 环境探测                [OK] CDSROOT 已识别, 75+ batch commands
TEST  2: Allegro .brd 扫描       [OK] 找到 N 个 .brd 文件
TEST  3: SPICE 网表生成          [OK] .TRAN / .END / 文件已保存
TEST  4: 电路 DSL 解析           [OK] 识别元件、控制指令
TEST  5: 生成 OrCAD DSN 文本     [OK] XML 写入成功
TEST  6: SPICE → Allegro 转换    [OK] 包含 R1 / C1 等 refdes
TEST  7: 安全命令清单            [OK] 56+ 命令白名单
TEST  8: allegro_batch help 调用 [OK] exit=0
TEST  9: MCP 工具注册表          [OK] 13 tools / 13 handlers
TEST 10: 端到端电路设计流程      [OK] .cir / .tel / .dsn 全部产出

Live MCP demo

For a real MCP-protocol walkthrough (spawns the server, calls every tool via JSON-RPC stdio, shows actual outputs and writes real files):

python demo_mcp_live.py

Expected outcome: all 14 tasks succeed; produces _demo_rc.cir, _demo_div.cir, _demo_step.cir, _demo_rc.tel, _demo_amp.dsn in examples/.

For just the simulation numeric results without MCP overhead:

python demo_summary.py

🧩 End-to-End Example

Tell your AI assistant:

"Design a low-pass RC filter with fc=160 Hz and simulate it."

The AI calls, in order:

1. cadence_probe                       # learn environment
2. list_simulation_templates           # see what's available
3. generate_spice_netlist              # template=rc_lowpass, fc≈160Hz
4. run_circuit_simulation              # execute on PSpice/ngspice
5. netlist_to_allegro                  # convert for PCB layout
6. allegro_batch_run subcommand=netin  # import into Allegro

Output flow:

ai_design.cir    PSpice/ngspice  →  ai_design.out (measurements)
ai_design.tel    SPICE → Allegro  →  ready for `allegro_batch netin`
ai_design.dsn    OrCAD Capture   →  optional: hand-edit in Capture

🔧 Simulation Backends

The server auto-selects the best available backend in this order:

Priority

Backend

Requirements

1

pspice.exe -b

PSpice on PATH + valid license

2

ngspice -b

ngspice on PATH (download separately)

3

analytical-rc

Built-in numpy solver for RC / divider / step (no deps)

4

analytical-divider

Closed-form R1+R2 voltage divider

Auto-skip behavior: if cadence_probe reports license_present: false, the server skips PSpice automatically (avoids the 60s timeout) and goes straight to the analytical fallback. So you get instant simulation results even without any license.

Tested backends:

  • PSpice binary present at C:\Cadence\SPB_23.1\tools\bin\pspice.exe; -b mode requires an active license. When license is missing, server falls back gracefully.

  • ngspice is the recommended open-source fallback. Download from https://ngspice.sourceforge.io/download.html and put ngspice.exe on PATH. (On some networks SourceForge blocks direct downloads; try MSYS2 mingw-w64-ucrt-x86_64-ngspice instead.)

  • PySpice 1.5 Python wrapper is auto-detected (pyspice_available: true).

  • Analytical fallback (numpy only) — solves RC low/high-pass, step response, and voltage dividers in closed form / closed-form-plus-numerical. Always available, no external binaries required.

Demonstrated simulation results (no license required)

Run python demo_summary.py:

RC 低通滤波器 (rc_lowpass)     Vout_peak=4.36V   tau=100μs   fc=1.59kHz
RC 高通滤波器 (rc_highpass)    Vout_peak=4.36V   tau=100μs   fc=1.59kHz
RC 阶跃响应  (rc_step)         Vout_end=0.48V    tau=10ms    fc=15.9Hz
电压分频器   (voltage_divider) Vout=8.0V  (Vin=12V, R1=1k, R2=2k)

🛡 Security & Sandboxing

  • All external commands run through subprocess.run with hard timeout.

  • allegro_batch_run enforces a 56-command allow-list unless allow_unsafe=true is explicitly set.

  • File I/O paths are normalised; netlist files are written with ASCII encoding to avoid encoding edge cases.

  • No network calls; pure local execution.

  • License state is reported (license_present: false/true) but never assumed.


📚 Reference: Useful Allegro Batch Subcommands

Selected from the 75+ available:

Command

Purpose

artwork

Generate Gerber photoplot files

netin

Import netlist into board

netrev

Forward-annotate schematic changes

report

Generate design reports (DRC, BOM, etc.)

dump_libraries

Extract padstacks, symbols, devices from board

brd2dml

Convert .brd to DML (Design Markup Language)

convert_gerber

Convert Gerber format versions

ipc2581_out/in

IPC-2581 manufacturing data exchange

odbpp_out/in

ODB++ manufacturing data exchange

dfmwebextract

DFM web extraction for fabrication

perf_reports

Performance / signal-integrity reports

qvextract

Quantus verification extraction

placement

Component placement (constraint-driven)

swap

Component / pin swap

Run allegro_batch.exe help on your machine to get the full list.


🤝 Contributing

PRs should:

  1. Run python tests/test_all.py cleanly (no failures).

  2. Add tests for any new tool.

  3. Update this README's tool table.

  4. Keep the allow-list curated — every batch command added must be safe.


📄 License

MIT — see LICENSE.


CadenceAI MCP is the first combined schematic + PCB + simulation MCP for the Cadence SPB toolchain.

Available Tools

13 tools
allegro_batch_commandsA

列出 Allegro batch 支持的所有命令 (75+ 条).可用于了解 Allegro 批处理能力,挑选合适的工具做 Gerber 转换、网表导入、库导出、光绘生成等。

Inputs: no named parameters.

allegro_batch_runB

执行单个 allegro_batch 子命令 (如 artwork / netin / dump_libraries / report / brd2dml 等)。带白名单 (60+ 安全命令) 和超时保护,默认禁止高危操作。

Inputs: subcommand (required), args, timeout, allow_unsafe.

cadence_env_varsA

返回当前进程可见的 Cadence 相关环境变量快照(CDSROOT / CDS_LIC_FILE / LM_LICENSE_FILE 等)。用于诊断 license / 路径配置问题。

Inputs: no named parameters.

cadence_probeA

探测系统中的 Cadence EDA 工具链可用性,返回 SPB 根目录、可执行文件、license 状态、PSpice 模型库路径、Allegro 批处理命令清单等。这是新会话的第一调用,了解环境。

Inputs: cds_root.

find_brd_filesB

在指定根目录递归查找 Cadence Allegro PCB 文件 (.brd)。返回带元数据 (大小、估计层数、器件数) 的列表。

Inputs: root (required), glob, max_results.

generate_schematic_dsnB

基于组件与网络清单生成 OrCAD Capture 兼容的简化 .DSN 工程文本(纯 XML)。适合作为 AI 原理图设计的中间产物,再导入 Capture 进行后处理。

Inputs: nets (required), components (required), title, save_path, +1 more.

generate_spice_netlistC

基于模板 (rc_lowpass / rc_highpass / rlc_bandpass / voltage_divider / diode_rectifier / rc_step_response) 或直接 DSL 生成 PSpice / ngspice 兼容的电路网表,并保存到指定路径。

Inputs: template, save_path, custom_dsl, parameters.

list_simulation_templatesB

列出所有可用的电路仿真模板及默认参数,方便 AI 选型。

Inputs: no named parameters.

netlist_to_allegroA

把 SPICE 网表转换成 Allegro netin 接受的简化物理网表 (.tel 风格)。适合 netin 工具的预处理步骤。

Inputs: spice_netlist (required), save_path.

parse_brd_fileA

从 .brd 文件中提取可读字符串片段,作为 PCB 设计的轻量级上下文(层、器件、网络、规则等)。适合作为 AI 摘要的输入,不能替代完整 Allegro DB 解析。

Inputs: brd_path (required), max_bytes.

parse_circuit_dslB

把类 SPICE DSL 文本解析为结构化数据 (组件清单、节点、控制指令),便于 AI 理解电路结构。

Inputs: dsl (required).

run_circuit_simulationA

执行电路仿真。自动选择后端:1) 找到 pspice.exe 就用 PSpice (Cadence 默认需 license);2) 否则尝试 ngspice CLI;3) 都没有就只返回网表 + 安装提示。返回 measurements (峰值/平均/RMS) 与 trace 名称。

Inputs: netlist (required), analysis, work_dir, prefer_pspice.

safe_batch_commandsA

返回 allegro_batch 的白名单命令列表(无需 GUI license 即可使用的安全子命令)。

Inputs: no named parameters.

Tool Schema Changelog

Recent tool additions, removals, and schema changes observed during successful MCP inspections.

Loading tool schema changelog…

    TDQS

    A3.6/5.0

    Scored across 13 tools

    Disambiguation4/5

    Most tools target distinct actions/resources (parse, find, run, generate), but cadence_probe vs cadence_env_vars and allegro_batch_commands vs safe_batch_commands have overlapping diagnostic/listing purposes. Descriptions clarify the differences, so an agent can usually disambiguate.

    Naming Consistency4/5

    All names use snake_case, which is consistent. However, the set mixes verb_noun patterns (parse_circuit_dsl, generate_spice_netlist) with noun phrases (cadence_probe, allegro_batch_commands), so it is not a perfect single convention.

    Tool Count5/5

    13 tools is well within the ideal 3-15 range for a specialized EDA assistant. Each tool appears to cover a distinct step in the Cadence workflow, from discovery to simulation.

    Completeness4/5

    The surface covers environment probing, file discovery, DSL/netlist generation, batch execution, and simulation. Minor gaps remain around direct .brd mutation and deeper Allegro database editing, but core AI-assisted workflows are supported.

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