generate_bitstream
Creates an FPGA bitstream from an implemented Vivado design, enabling device programming after synthesis and implementation.
Instructions
Generate bitstream for the implemented design
Tool call template
This tool declares no required parameters. Add optional parameters from the input schema as needed.
{
"id": 1,
"jsonrpc": "2.0",
"method": "tools/call",
"params": {
"arguments": {},
"name": "generate_bitstream"
}
}Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||