logisim271-mcp
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- AlicenseNot gradedqualityCmaintenanceEnables MCP clients to build Logisim circuits from natural language by adding pins, gates, LEDs and wires through tools that return exact port coordinates, then saving the result as a .circ file. It also runs Logisim's own loader to read the file back and report dangling wire ends and multi-driver shorts.MIT
- AlicenseAqualityCmaintenanceLocal electronics tools for MCP-capable assistants, enabling static analysis of CRUMB save files and Logisim-evolution projects, including net tracing, BOM building, electrical rule checks, and optional truth table generation.2288 npm1Apache 2.0
- AlicenseNot gradedqualityDmaintenanceA local MCP server for working with Logisim-evolution .circ projects, providing structured project inspection, guarded edits, validation, circuit analysis, test execution, format conversion, and GUI launch.2MIT
- AlicenseAqualityCmaintenanceEnables Claude to draw, simulate, and verify Logisim-evolution 5 circuits directly from natural-language descriptions, without opening the GUI — it lays out components, routes wires, and returns images of the resulting .circ files. It also synthesizes circuits from formulas or truth tables (minimizing to MDNF/MKNF and converting to NAND/NOR bases), detects wiring faults, and checks behavior against expected outputs or clock sequences.92GPL 3.0
- AlicenseNot gradedqualityBmaintenanceEnables AI agents to build, wire, inspect and simulate digital circuits directly in a running Logisim Evolution window, with every edit appearing live and undoable. Agents work from exact ports, real netlists and truth tables rather than screenshots, and can verify designs through simulation.2MIT
- AlicenseBqualityCmaintenanceEnables an AI to build, inspect, test, and render logic circuits as .dig files, then open them in the Digital app.10GPL 3.0
TDQS
Scored across 21 tools
Most tools target a clearly distinct action+resource: add_pin/add_gate/add_component/add_constant/add_wire/add_subcircuit_instance are separable, and the three build_* tools differ by input form (expressions, presets, truth table). The main overlap is in the simulation family — simulate, truth_table, simulate_sequential, and verify_truth_table share concepts, and build_logic vs build_from_truth_table could be misselected by an agent that doesn't read carefully.
The dominant convention is verb_noun (create_circuit_file, list_circuits, add_gate, delete_circuit, write_ram_image), which is applied broadly across circuit, component, and simulation tools. Minor deviations exist: bare 'remove', bare 'simulate', and the noun-only 'truth_table', plus 'create_circuit_file' vs 'add_circuit' showing two different verbs for placing a circuit.
21 tools is on the high side of the acceptable band, but the domain (layout editing, synthesis, and simulation of digital circuits) genuinely requires this breadth. Each tool covers a distinct capability, so little feels redundant, though a few simulation tools could conceivably be merged.
Coverage is strong: project creation, circuit lifecycle (add/list/delete/set_main), component placement and wire routing, removal, high-level builders, and multiple simulation/verification modes including sequential and RAM images. Gaps are minor — no tool to rename or edit existing component properties (e.g., change a gate's input count or relabel), and no explicit open/load of an external .circ path beyond what list/describe imply.