Export circuit connectivity with the original compiler
netlist_exportCopies a MAX+plus II design to a temp directory, compiles it with EDIF/VHDL/Verilog/AHDL writers, and returns hashes, compiler evidence, exported files and net connectivity while preserving originals.
Instructions
Copy a GDF/HDL/ACF/EDIF design and local dependencies to a fresh temporary directory; enable original MAX+plus II EDIF/VHDL/Verilog/AHDL writers and compile there. Return source hashes, actual compiler evidence, exported files and structured port/instance/net connectivity. Original files remain untouched. The netlist is synthesized logic; original drawing placement and source component identities can change. Supports async jobs and cancellation.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes | Source file relative to the project/workspace; absolute paths must remain within that scope. | |
| root | No | MAX+plus II installation root, default MAXPLUS2_ROOT/discovery. | |
| async | No | Return jobId immediately; poll job_status or stop with job_cancel. | |
| project | No | Existing ACF project to scope file paths to its directory. | |
| timeoutMs | No | Compiler timeout; default 60000 milliseconds. | |
| workspace | No | Workspace scope when project is omitted; defaults to MAXPLUS2_WORKSPACE. |