validate_netlist
Catch common errors in LTspice netlists and schematics before simulation: element arity, duplicate directives, bad .MEAS patterns, floating pins. Returns structured issue list.
Instructions
Lint a netlist or schematic before simulation — the static circuit check gate. Catches: element arity (too few nodes, missing E/G/F/H/B value), duplicate/multiple analysis directives ('More than one analysis specified'), .MEAS whose analysis kind isn't present, known-bad .MEAS patterns (vdb()/phase()/group_delay()), and directives the LTspice runner is known to reject. On .asc, also surfaces named-net shorts, floating pins, and dangling labels. Returns a structured issue list; an empty list means the file passes the static gate. Note: value tokens (e.g. a typo'd '1kk') and undefined model references are NOT checked — LTspice coerces or resolves those at run time.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes | Path to circuit file (.cir, .net, or .asc) | |
| format | No | Response format: 'json' for structured data, 'text' for human-readable |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| file | No | ||
| issue_count | No | ||
| issues | No |