An MCP server for FPGA toolchain operations including linting, simulation, synthesis, place-and-route, bitstream programming, and IP core registry via GitHub.
A minimal MCP server that provides 25 tools and 5 hooks to control Xilinx Vivado EDA for FPGA development, including session management, Tcl execution, smart diagnostics, and IP debugging.
MCP server that equips AI agents with BSV-specific development tools including static analysis, pitfall prediction, and BSC error diagnosis to produce correct Bluespec code with fewer compile failures.
An MCP server that provides AI assistants with a persistent, sandboxed Python environment for waveform analysis, enabling loading and manipulation of VCD/FST/FSDB files and temporal pattern matching.
A comprehensive Model Context Protocol server that connects AI assistants to Electronic Design Automation tools, enabling Verilog synthesis, simulation, ASIC design flows, and waveform analysis through natural language interaction.
MCP server for deterministic Vivado FPGA automation including project scaffolding, simulation, synthesis, implementation, and gated bitstream generation.