Enables AI coding agents and IDEs to prove SystemVerilog assertions with SymbiYosys (smtbmc+z3) and lint SVA syntax, returning honest verdicts such as PROVEN, FAILED, UNKNOWN, ERROR, or TIMEOUT.
Enables AI coding agents to discover, generate, and run Cocotb co-simulation testbenches against Verilog/SystemVerilog designs, returning structured pass/fail results and tracebacks without manual simulator or Makefile setup.