A
licenseNot graded
qualityC
maintenanceGives coding agents structured access to an EDA toolchain so they can lint, simulate, formally verify, synthesize, place and route, program a board and read its UART. Returns parsed results (errors with file and line, timing per clock, utilization, inferred memories, counterexample traces) instead of raw logs, closing the run-simulate-fix loop without copy-paste.
11
AGPL 3.0