"author:chinn-choppa" matching MCP servers:

Enables local analysis of FPGA synthesis diagnostics and Synopsys Synplify Pro reports, including parsing diagnostic messages and comparing warnings, resources, and preliminary timing reports across builds. It currently provides a limited prototype with read-only server and tool status and does not run synthesis or simulation.

Provides a portable local MCP interface for RTL simulation, diagnostics, and verification workflows with Verilator, currently exposing server information, tool discovery, and bounded text diagnostic parsing while lint and simulation execution remain planned.

Enables MCP clients to inspect server state, detect an installed Questa/ModelSim simulator without launching it, and extract diagnostic messages from simulation text output. It provides a scaffold toward deterministic regression runs and waveform analysis, but does not yet execute synthesis or simulation.