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Enables AI coding agents and IDEs to perform AST-backed semantic Verilog/SystemVerilog code reviews, catching race conditions, reset polarity mismatches, and bitwidth truncations while computing a 0–100 RTL quality score.

Enables AI coding agents and IDEs to lint, compile, syntax-check, and simulate Verilog/SystemVerilog designs through structured, token-efficient MCP tools with isolated containerized toolchains.

Enables AI coding agents and IDEs to prove SystemVerilog assertions with SymbiYosys (smtbmc+z3) and lint SVA syntax, returning honest verdicts such as PROVEN, FAILED, UNKNOWN, ERROR, or TIMEOUT.

Enables AI coding agents and IDEs to synthesize Verilog/SystemVerilog designs with Yosys, inspect cell hierarchies and gate counts, and detect synthesis hazards like inferred latches and combinational loops before physical design flows.