Check the RF toolchain on this machine before trusting any result.

Reports the AEDT install PyAEDT will drive, the Python packages the loop needs, and whether a live Altium bridge is reachable. Call this first when anything behaves oddly.

The parametric structures this server can synthesise and optimise.

Grounded-CPW impedance, effective permittivity and wavelength.

Give width_mm to analyse a line, or z0 to synthesise the width that hits an impedance. This is the closed-form model the optimiser seeds from -- it is accurate enough to start from and not accurate enough to finish on.

Turn a requirement into the structured spec everything else reads.

Limits are stated the way a datasheet states them: s11_db=-20 means S11 at or below -20 dB across the band, isolation_db=-18 means the coupling between any two outputs stays at or below -18 dB. Keep requirement_text -- it goes in the report so the design can be traced back to the sentence that asked for it.

Draw a candidate layout without solving it.

With no params this returns the analytic seed -- the textbook starting point the optimiser begins from. Always cheap; use it to sanity-check dimensions, DRC and board size before committing solver time. The PNG is worth looking at.

Solve one candidate in HFSS and score it against the spec.

Blocking, and a full-fidelity solve on a small divider is minutes. Use draft=True for a fast, coarser answer. Results are cached by geometry content, so re-solving the same candidate is free.

Start an Optuna study over the device's parameters, scored by HFSS.

Returns a job id immediately; poll rf_job_status. Trial 0 is always the analytic seed. Exploration runs at draft mesh; call rf_design instead if you want the winner verified, exported and reported in one go.

Run the whole closed loop: seed, optimise, verify, export, report.

Returns a job id; poll rf_job_status. The winner is re-solved at full fidelity before anything is reported, and if rounding the trace widths onto Altium's 1-mil grid shifts an impedance, the snapped geometry is solved too so the report states what the board will actually do rather than what the optimiser found.

write_altium=True commits the result into the PCB the user has open, which needs a live eda-agent bridge -- check rf_doctor first.

Progress of a running study or design loop, and its result when done.

Every job this server has run in this session.

Is a live Altium session reachable, with a PCB open and ready to write?

Says which of the three things is missing -- eda-agent not importable, Altium not running, or the bridge script not started inside it -- and how to fix that one.

Write a design into the PCB document the user currently has open.

Emits design intent, not EM polygons: centrelines as tracks with their real widths, ground vias as vias, and the coplanar ground as a polygon pour with a clearance rule sized to the gap the EM model used.

dry_run=True (the default) resolves the whole plan to mils and returns it without touching the board. Look at the quantisation report before committing -- Altium's PCB command surface is integer mils, and on a narrow high-impedance arm that rounding moves the impedance.