Enables AI assistants to control Cadence Xcelium and SimVision simulators in real time for automated RTL and gate-level debugging. It provides 25 tools for signal inspection, watchpoints, binary search, and simulation state management.
Enables AI assistants to analyze RTL simulation and synthesis logs through deterministic tools for compile-log summaries, signal tie-off safety checks, and regression result statistics.
An MCP server that provides AI assistants with a persistent, sandboxed Python environment for waveform analysis, enabling loading and manipulation of VCD/FST/FSDB files and temporal pattern matching.
Enables RTL simulation and hardware verification with Verilator through automatic testbench generation, natural language queries about simulations, waveform analysis, and protocol-aware testing for Verilog/SystemVerilog designs.
MCP server that diagnoses ML model regressions by correlating drift reports, eval runs, and deploy logs, providing evidence-cited incident reports through a set of investigation tools.
