Store a SPICE netlist and return a circuit ID for subsequent analyses.

Run AC analysis on a stored circuit.

Run transient analysis on a stored circuit.

Run DC operating point analysis on a stored circuit.

Return the last simulation results for a circuit.

Delete a stored circuit and clean up its output directory.

Generate a schematic diagram from a stored circuit's netlist.

When a schematic_url is present in the response, ALWAYS include it as a clickable link in your message to the user. Users cannot see inline images. The schematic_url in the response is a public internet-accessible URL, not a sandbox or localhost URL. Always share it directly with the user.

Export circuit as KiCad 8 schematic (.kicad_sch) file.

Start the interactive web schematic viewer and return its URL.

Store port definitions for a circuit.

ports maps port names to netlist node names, e.g. {"in": "in", "out": "out", "gnd": "0"}.

Return port definitions for a circuit, auto-detecting if none are set.

Compose multiple circuit stages into a single combined circuit.

Each element of stages is {"circuit_id": str, "label": str (optional)}. If connections is omitted, stages are auto-wired in order (out of stage N → in of stage N+1). shared_ports defaults to ["gnd"] — those nodes are never prefixed.

List available circuit templates, optionally filtered by category.

Load a circuit template and create a circuit from it.

If specs is provided, the design-equation solver runs automatically, results are snapped to E24 standard values, and the netlist .param lines are updated. Explicit params override solver-calculated values.

Modify a component value in a stored circuit's netlist.

Validate the netlist syntax of a stored circuit using ngspice.

Measure the bandwidth (cutoff frequency) of an AC analysis result.

Uses -3dB by default; specify threshold_db for custom cutoff levels.

Measure gain and phase at a specific frequency from AC analysis results.

Measure the DC voltage at a specific node from operating point results.

Extract key transient response metrics (rise time, settling time, overshoot).

Measure power consumption from DC operating point results.

Compare simulation results against design specifications.

specs format: {"spec_name": {"target": N, "tolerance_pct": P}} or {"spec_name": {"min": N, "max": M}}.

Calculate component values for a circuit topology from target specs.

Run the full design loop in one call: load template, simulate, and verify.

specs uses compare_specs format: {"f_3dB_hz": {"target": 1000, "tolerance_pct": 5}}

sim_type is one of "ac", "transient", or "dc". sim_params optionally overrides default simulation parameters.

Returns accumulated results including circuit_id, simulation data, measurements, and spec comparison. On failure at any step, returns partial results with an error key and failed_step.

When a schematic_url is present in the response, ALWAYS include it as a clickable link in your message to the user. Users cannot see inline images. The schematic_url in the response is a public internet-accessible URL, not a sandbox or localhost URL. Always share it directly with the user.

Generate a SPICE .lib model file from datasheet parameters.

component_type: "opamp", "bjt", "mosfet", "diode" name: model name (e.g. "OPA2134") parameters: type-specific datasheet values; omitted keys use defaults.

Return all saved SPICE models from the model library.

Run Monte Carlo analysis under component tolerances.

Randomly varies R/C/L component values within tolerance bands and runs multiple simulations to produce statistical results.

analysis_type: "ac", "transient", or "dc_op" tolerances: map component ref or prefix (R/C/L) to tol %.

Run worst-case analysis at tolerance extremes.

Evaluates component sensitivity and deterministic corner combinations to find true worst-case performance bounds.

analysis_type: "ac", "transient", or "dc_op" tolerances: map component ref or prefix (R/C/L) to tol %.