design_commit
Compose and visually review the schematic, run ERC gating, then commit the validated design state to the PCB workflow.
Instructions
Compose + visual-review + ERC-gate the schematic, then commit semantic state.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
No arguments | |||
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |