review_board
Check a KiCad PCB for DRC, unrouted nets, zone fill, outline, fab limits, power track widths, stitching, and decoupling, reporting PASS, WARN, FAIL or UNVERIFIED with evidence.
Instructions
Review a board the way a fab and a layout reviewer would: DRC and unrouted connections, zone fill state, footprints outside the outline, manufacturability against the fab's published limits (tracks, vias, annular rings, hole spacing, edge clearance, silkscreen), track widths on power nets, zone stitching, and decoupling capacitor distance. Every check reports PASS, WARN, FAIL or UNVERIFIED with its evidence and the source of its limits.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| fab | No | Whose manufacturing limits to check against. jlcpcb picks 2- or 4-layer limits from the board. | jlcpcb |
| board_path | Yes | A .kicad_pcb file, absolute or relative to the workspace. | |
| schematic_parity | No | Include DRC's schematic parity check when a schematic exists. |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| fab | No | ||
| kind | Yes | ||
| checks | Yes | ||
| counts | Yes | ||
| target | Yes | ||
| verdict | Yes | Worst verdict of the checks that ran. Unverified checks are listed separately and never hidden. | |
| duration_s | Yes | ||
| unverified | No | Checks that could not run, with their reasons in the check summaries. |