digital_export_simulation_image
Simulate a Digital logic circuit with custom input states and export a high-resolution SVG or PNG snapshot of the rendered model, enabling visual verification without a GUI.
Instructions
Apply input/button states such as {A: 1, B: 0}, render the live Digital model, and export a high-resolution SVG or PNG snapshot. The circuit is simulated headlessly; the GUI is not driven.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| path | Yes | ||
| scale | No | ||
| format | No | png | |
| inputs | No | ||
| hide_test | No | ||
| output_path | No | ||
| pixel_width | No | ||
| timeout_seconds | No |