simulate_verilog
Execute Verilog code simulation with Icarus Verilog to test hardware designs using provided design and testbench code.
Instructions
Simulate Verilog code using Icarus Verilog
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| verilog_code | Yes | The Verilog design code | |
| testbench_code | Yes | The testbench code |
Implementation Reference
- src/index.ts:225-265 (handler)Core handler function for 'simulate_verilog' tool. Creates a temporary project directory, writes the provided Verilog design and testbench code to files, compiles using iverilog, executes the simulation, captures compile and simulation outputs, and returns a JSON object with results including a project_id for subsequent waveform viewing.
async simulateVerilog(verilogCode: string, testbenchCode: string): Promise<string> { try { const projectId = Math.random().toString(36).substring(2, 15); const projectDir = join(this.tempDir, `sim_project_${projectId}`); await fs.mkdir(projectDir, { recursive: true }); // Store project info this.projects.set(projectId, { dir: projectDir, type: "simulation" }); // Write design and testbench files await fs.writeFile(join(projectDir, "design.v"), verilogCode); await fs.writeFile(join(projectDir, "testbench.v"), testbenchCode); // Compile and run simulation const compileCmd = `iverilog -o simulation design.v testbench.v`; const { stdout: compileOut, stderr: compileErr } = await execAsync(compileCmd, { cwd: projectDir, timeout: 60000, }); const { stdout: simOut, stderr: simErr } = await execAsync('./simulation', { cwd: projectDir, timeout: 60000, }); return JSON.stringify({ project_id: projectId, success: true, compile_stdout: compileOut, compile_stderr: compileErr, sim_stdout: simOut, sim_stderr: simErr, note: `Use view_waveform with project_id: ${projectId} to open GTKWave` }, null, 2); } catch (error: any) { return JSON.stringify({ success: false, error: error.message || String(error), }, null, 2); } } - src/index.ts:752-765 (schema)Input schema for the 'simulate_verilog' tool, defining required string parameters 'verilog_code' and 'testbench_code'.
inputSchema: { type: "object", properties: { verilog_code: { type: "string", description: "The Verilog design code" }, testbench_code: { type: "string", description: "The testbench code" }, }, required: ["verilog_code", "testbench_code"], }, - src/index.ts:749-766 (registration)Tool registration entry in the ListToolsRequestSchema handler, defining name, description, and input schema for 'simulate_verilog'.
{ name: "simulate_verilog", description: "Simulate Verilog code using Icarus Verilog", inputSchema: { type: "object", properties: { verilog_code: { type: "string", description: "The Verilog design code" }, testbench_code: { type: "string", description: "The testbench code" }, }, required: ["verilog_code", "testbench_code"], }, }, - src/index.ts:880-890 (registration)Dispatch handler in CallToolRequestSchema switch statement: validates input arguments and invokes edaServer.simulateVerilog method.
case "simulate_verilog": { const verilogCode = validateRequiredString(args, "verilog_code", name); const testbenchCode = validateRequiredString(args, "testbench_code", name); return { content: [{ type: "text", text: await edaServer.simulateVerilog(verilogCode, testbenchCode), }], }; }