load_design
Load a gate-level netlist with Liberty libraries, top module, and optional SDC constraints into OpenSTA to enable timing analysis. Returns per-step timings and warnings.
Instructions
Load a design into the OpenSTA session. Call this once before any analysis.
liberty: Liberty (.lib) file path, or a list of paths verilog: gate-level netlist (.v) path top: top module name to link sdc: SDC constraints file (optional but required for meaningful timing) spef: parasitics file (optional; without it delays use wire-load / no parasitics)
Returns per-step timings and a digest of warnings. Warnings raised here (unmatched SPEF nets, missing cells, unconstrained ports) affect every later result, so read them. Starts a new analysis state (see get_conditions). Loads on top of the running sta: to drop earlier constraints and run_tcl changes, call restart_session first.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| sdc | No | ||
| top | Yes | ||
| spef | No | ||
| liberty | Yes | ||
| verilog | Yes |
Output Schema
| Name | Required | Description | Default |
|---|---|---|---|
| result | Yes |