Solve a PCB stackup
run_stackup_solverRead-only
Run the impedance-aware stackup constraint solver to find optimal PCB configurations. Use when the user wants ranked material/thickness/copper solutions for a given layer count and frequency. Returns scored and ranked feasible stackups. Each solution's prepreg_thickness_mm is the catalog BASE (pre-lamination) ply thickness, so the per-ply numbers do NOT sum to total_thickness_mm — the total uses the pressed thickness, 0.04064 mm thinner per prepreg ply. Report both as returned; never 'correct' one to match the other.
Input Schema
TableJSON Schema
| Name | Required | Description | Default |
|---|---|---|---|
| topology | No | Transmission line type: microstrip or stripline (default microstrip) | |
| build_type | No | Lamination build: 'single' (default) or HDI level hdi1-hdi4. HDI defaults cost_priority to performance. | |
| layer_count | Yes | Total copper layers (even number, 2-32) | |
| solder_mask | No | Solder mask covering the OUTER trace, as {thickness_mm, dk}. Mask raises the effective permittivity around the trace and pulls Z0 down, so the solver returns a NARROWER width for the same target impedance. OMIT IT (the default) and the microstrip is solved BARE — pass it only when the user says the outer traces are mask-covered, or states a mask thickness or mask Dk. Applies to microstrip targets only: a stripline is buried under laminate, not mask. Both members are optional and default to typical green LPI (0.02 mm, Dk 3.5); thickness_mm must be over 0 and at most 0.2, dk over 1 and at most 10. Mask LOSS is not modeled: the insertion-loss score leaves it out, and a masked result says so in diagnostics — tell your user when you cite a masked solve. | |
| construction | No | Lamination. OMIT it unless the user named one: an omitted lamination is built core_outer wherever core outer can be built (4+ layers, build_type 'single') and foil everywhere else (2 layers, any HDI build). 'foil' puts prepreg outermost, so an outer microstrip rides on prepreg; 'core_outer' puts a core outermost, so the core material, such as an RF laminate, sits directly under the outer microstrip — the same choice Guided Phase IV offers. 'auto' searches BOTH and ranks them together; send it only when the user asks to compare the two. Core outer makes EVERY core that material (N/2 cores), not only the outer pair. Each solution reports the construction it was built as; name it when you cite that solution. | |
| user_request | No | The end user's own words that prompted this call, verbatim. Used to verify that the figures you pass were stated by your user rather than inferred. Omit it and the results will be labelled caller-asserted. | |
| cost_priority | No | Cost preference: low, balanced, or performance. Default balanced; an HDI build_type OR a frequency at or above 18 GHz defaults to performance instead, because at mm-wave a balanced weighting ranks an FR4-class laminate above every low-loss one. Pass it explicitly to override either default — a stated preference always wins. The priority actually used comes back as costPriority. | |
| frequency_ghz | Yes | Operating frequency in GHz | |
| max_solutions | No | Max solutions to return, 1-20 (default 5) | |
| impedance_ohms | No | Target impedance in Ohms (default 50). Single-target convenience — ignored when impedance_targets is given. | |
| reflow_process | No | Assembly reflow process; enforces a Tg floor on all dielectrics (default lead_free). | |
| copper_weight_oz | No | Restrict solutions to this copper weight in oz (0.5, 1, 2, or 3). Omit to let the solver optimize copper weight; an omitted value inherits the latest update_stackup_config copper weight automatically. The value is the FINISHED thickness, with outer-layer plating already included (1 oz = 0.035 mm finished, plated up from 0.5 oz starting foil). A spec written as '0.5 oz base foil + plating, 1.7 mil finished' uses the OTHER convention — pass 1, not 0.5. | |
| impedance_targets | No | Up to 4 impedance targets the stackup must satisfy SIMULTANEOUSLY, each {ohms, topology ('microstrip'|'stripline'), differential (bool), spacing_mm (differential pair gap in mm, default 0.15)}. Use for multi-impedance boards — e.g. 50 ohm RF plus a 100 ohm differential pair. Overrides impedance_ohms/topology. | |
| target_thickness_mils | No | Board thickness in mils (default 62) | |
| allowed_core_materials | No | Restrict core dielectrics to these catalog materials (e.g. RO4350B, MEGTRON6). Pass ONLY materials the user named; omit to search the full catalog. | |
| thickness_tolerance_mm | No | Allowed deviation from the target thickness in mm. OMIT it and the solver uses 10% of the target thickness. Set it only when the user states a tolerance. The value the solve used comes back as thicknessToleranceMm - cite that one. | |
| allowed_prepreg_materials | No | Restrict prepregs to these catalog materials (e.g. RO4450F, MEGTRON6). Pass ONLY materials the user named; omit to search the full catalog. |