Set design rules
set_design_rulesSet the project design rules (.kicad_pro) and copper layer count. Works on a board workspace and on a generated design (create_design → start_board). On a generated design the rules go into circuit.kicad_pro/.kicad_dru in place (the previous ones are snapshotted under rules_revisions/), are kept by every later project write (project.zip, a new board run), the copper is not changed and KiCad DRC judges the board against them at once: the reply carries the DRC counts and whether the Gerbers are released; the next start_board routes to the default_* values. copper_layers, stackup and board_thickness_mm are workspace-only (a generated design changes them with a new board). preset "jlcpcb" applies JLCPCB's published minimums for the layer count and writes their per-feature limits (plated rings, pad hole spacing, hole-to-track) as KiCad custom rules (.kicad_dru) that run_drc checks; explicit values override the minimums. Board minimums (min_*), the Default net class (default_*), and named net classes with their net patterns. route_board routes with these rules and run_drc checks against them. Changing copper_layers rebuilds the stackup; tracks on removed layers are reported. copper_layers 1 is a single-sided board (hand etching): the KiCad file keeps F.Cu and B.Cu, and from then on the routers hold to one face (B.Cu as soon as a THT pad exists, else F.Cu) and place no via; copper on the other face is removed.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| preset | No | ||
| wait_s | No | Seconds to wait for the job (default 55). A job still running comes back with status "running": follow it with get_board_job. | |
| stackup | No | JLCPCB's 4-layer 1.6 mm impedance stackups, written into the board: 7628 (0.21 mm prepreg, their default) or 3313 (0.1 mm prepreg: thinner pairs for the same impedance). Needed before a net class states diff_impedance_ohm. | |
| design_id | Yes | The design id returned by import_kicad_project or list_designs. | |
| net_classes | No | ||
| min_track_mm | No | ||
| copper_layers | No | ||
| hole_to_hole_mm | No | ||
| default_track_mm | No | ||
| min_clearance_mm | No | ||
| hole_clearance_mm | No | ||
| board_thickness_mm | No | Finished board thickness; the stackup is rebuilt to it. JLCPCB FR4: 0.4, 0.6, 0.8, 1.0, 1.2, 1.6, 2.0 mm. | |
| min_via_annular_mm | No | ||
| min_via_diameter_mm | No | ||
| default_clearance_mm | No | ||
| default_via_drill_mm | No | ||
| min_through_drill_mm | No | ||
| default_via_diameter_mm | No | ||
| copper_edge_clearance_mm | No |