Anneal a dense placement
anneal_placeDense placement by simulated annealing: wirelength inside the outline with courtyard gaps, edge connectors held on their edge, fixed and locked parts held, keepout rectangles kept clear (routing corridors), and a per-pad price for the bottom side (flip_cost, mm of wirelength; each bottom-side pad whose net has top-side pins costs a via). Starts from the current positions unless from_scratch. Slower than auto_place (a minute per 600k iterations) and much denser. Check overlapping_pairs and run_drc afterwards.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| t0 | No | Start temperature (default 15). ~0.5 keeps the current placement and only tidies it (refine, or squeeze into a smaller outline). | |
| edge | No | Connector ref to the edge it sits on, optionally @mm: where along that edge its centre goes, from the outline's top-left corner (x on top/bottom, y on left/right) — the same meaning as in auto_place and a board plan. A fixed or locked ref keeps its pin. | |
| halo | No | Routing room per ref, mm (a number all round, or footprint-local [left, top, right, bottom]). | |
| refs | No | The footprints that may move (default: every unlocked one). | |
| seed | No | ||
| fixed | No | ||
| shove | No | Legaliser: a part may take a spot held only by movable parts under this fraction of its area (default 0.3, 0 off). | |
| gap_mm | No | ||
| wait_s | No | Seconds to wait for the job (default 55). A job still running comes back with status "running": follow it with get_board_job. | |
| grid_mm | No | Placement grid for free parts (0.254 = 10 mil, the designer habit); default off. | |
| keepouts | No | Rectangles no part may cover, e.g. a bus corridor. | |
| bottom_ok | No | Footprint-id substrings allowed on the bottom side (e.g. "0402"). | |
| design_id | Yes | The design id returned by import_kicad_project or list_designs. | |
| flip_cost | No | ||
| rotations | No | ||
| bottom_any | No | Any SMD-only part may go to the back (priced by flip_cost); LEDs, switches, displays and test points stay on top unless bottom_exclude says otherwise. | |
| ic_halo_mm | No | Room kept around ICs with 48+ pads (default 1.5). | |
| iterations | No | ||
| net_weight | No | ||
| refit_from | No | Outline the current placement was drawn in; it is scaled affinely into the new outline before annealing (with t0 ~0.5: shrink a placement that closed). | |
| split_cost | No | Price (mm of wirelength) of an SMD net with pads on both sides, i.e. a via. | |
| from_scratch | No | ||
| hole_room_mm | No | Room kept around mounting holes on both sides for the screw head and standoff (default 1). | |
| bottom_exclude | No | Regex of refs or footprint ids that stay on top regardless. | |
| overlap_weight | No | Overlap price per mm2 at the end of the anneal (default 400; 4000 halves what a dense draw leaves). | |
| edge_overhang_mm | No | Per edge ref, how far its body sits past the edge: default 0.5 for a USB/barrel/jack connector (at most its 1.2 mm lip), 0 (flush) for anything else, which may not overhang. | |
| connector_room_mm | No | Room kept on the board side of every edge connector (default 2.5). | |
| connector_flank_mm | No | Room kept on the flanks of every edge connector (default 1.0). | |
| bottom_max_height_mm | No | Tallest part allowed on the back (3D-model height, default 1.0): the assembly box grows by the tallest back-side part. |