Auto-place footprints
auto_placePack footprints inside the board outline with Koppar's heuristic placer (ratsnest-driven, courtyard-legal). By default every unlocked footprint moves and locked ones stay; refs names exactly which move (all others stay). Constraints: fixed (exact origin positions), side, keepouts (rectangles), groups, near (ref within maxMm of an anchor), edge (ref to "left|right|top|bottom"). Coarse by design: refine the result with place_footprints.
Input Schema
| Name | Required | Description | Default |
|---|---|---|---|
| edge | No | ||
| near | No | ||
| refs | No | The footprints that may move. | |
| side | No | ||
| fixed | No | ||
| shove | No | Legaliser: a part may take a spot held only by movable parts under this fraction of its area (default 0.3, 0 off). | |
| groups | No | ||
| placer | No | "ml": the learned placer service (dense, two-sided when two_sided, honours keepouts); the packer when it is unavailable. | |
| refine | No | "anneal": refine the placement by simulated annealing from this seed (wirelength-driven, same edge/fixed/keepouts, holes held) — the ML placer's structure with the annealer's tightness. | |
| wait_s | No | Seconds to wait for the job (default 55). A job still running comes back with status "running": follow it with get_board_job. | |
| grid_mm | No | Placement grid for the refine step (0.254 = 10 mil); default off. | |
| keepouts | No | ||
| bottom_ok | No | Refine: footprint-id substrings allowed on the back instead of bottom_any. | |
| design_id | Yes | The design id returned by import_kicad_project or list_designs. | |
| flip_cost | No | Annealing price per bottom-side pad whose net has top pins (default 3). | |
| two_sided | No | Small two-pad passives go to the back side. | |
| bottom_any | No | Refine: any SMD-only part may go to the back, priced by flip_cost (default with two_sided); LEDs, switches, displays and test points stay on top. | |
| ic_halo_mm | No | Refine: room kept around ICs with 48+ pads (default 1.5; 16+ pads and fine pitch get two thirds). | |
| iterations | No | Annealing iterations for refine (default 600000). | |
| split_cost | No | Refine: price (mm of wirelength) of an SMD net with pads on both sides, i.e. a via. | |
| hole_room_mm | No | Refine: room kept around mounting holes, both sides (default 1). | |
| bottom_exclude | No | Refine: regex of refs or footprint ids that stay on top. | |
| overlap_weight | No | Overlap price per mm2 at the end of the anneal (default 400; 4000 halves what a dense draw leaves). | |
| connector_room_mm | No | Refine: room kept on the board side of every edge connector (default 2.5). | |
| connector_flank_mm | No | Refine: room kept on the flanks of every edge connector (default 1.0); sets the pitch of connectors sharing an edge. | |
| bottom_max_height_mm | No | Refine: tallest part allowed on the back (3D-model height, default 1.0). |